University of California

Randy C Aceves

Paul G Carey

Patrick M Smith

Thomas W Sigmon

Jesse B Thompson

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250&deg; C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Thin film transistors on plastic substrates

A solar cell module lamination process using fluoropolymers to provide protection from adverse environmental conditions and thus enable more extended use of solar cells, particularly in space applications. A laminate of fluoropolymer material provides a hermetically sealed solar cell module structure that is flexible and very durable. The laminate is virtually chemically inert, highly transmissive in the visible spectrum, dimensionally stable at temperatures up to about 200&deg; C. highly abrasion resistant, and exhibits very little ultra-violet degradation.

Solar cell module lamination process

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

Growing community of inventors

Livermore, CA, United States of America

Randy C Aceves