International Business Machines Corporation

Globalfoundries Inc.

Lam Research Corporation

Stmicroelectronics Gmbh

Randolph F Knarr

Mahadevaiyer Krishnan

Balasubramanian Pranatharthiharan

Cyril Cabral, Jr

Christian Lavoie

Keith Kwong Hon Wong

Renee Tong Mo

Anna Wanda Topol

Jay William Strane

Kamalesh K Srivastava

Dechao Guo

Chengwen Pei

Sandra Guy Malhotra

Zhengwen O Li

Stephen Mark Rossnagel

Muthumanickam Sankarapandian

Roger Allan Quon

Vimal Kumar Kamineni

Jun Yuan

Sarah Huffsmith Knickerbocker

Xiaoyan Shao

Tien-Jen Cheng

Yanfeng Wang

Jian Yu

Jonathan H Griffith

Gan Wang

Philippe M Vereecken

Lisa A Fanti

David E Eichstadt

Georges Jacobi

Hariklia Deligianni

Wolfgang Sauter

Kevin Shawn Petrarca

Richard Paul Volant

Sunfei Fang

Stefan Schmitz

Rangarajan Jagannathan

Balasubramanian S Pranatharthi Haran

Horatio Seymour Wildman

Michael A Cobb

Bhaskar Nagabhirava

Michael Goss

Asa Frye

Prabhakara Gopaladasu

Peng Wang

Julie C Biggs

Gregory P Wandy

Adarsh Basavalingappa

Phil Friddle

Andrew P Mansson

Erik J Roggeman

Brent A Anderson

Edmund Juris Sprogis

Andrew Herbert Simon

Ahmet Serkan Ozcan

Yun-Yu Wang

Cornelius Brown Peethala

Emanuel Israel Cooper

Panayotis Constantinou Andricacos

Lindsey H Hall

Steven R Soss

Frank Wilhelm Mont

Christopher D Sheraw

Shariq Siddiqui

Brett H Engel

Jin Zheng Wallner

Filippos Papadatos

David F Hilscher

Lili Deligianni

Renee T c/o Ibm United Kingdom Limited Mo

Christian c/o Ibm United Kingdom Limited Lavoie

Jay W Strane

After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.

Method to recess cobalt for gate metal application

A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase.

Method for selectively etching with reduced aspect ratio dependence

An environmentally green wet etch process for selective removal of cobalt metal generally includes applying water that is free of added buffers, acids, and/or bases to a substrate including exposed cobalt metal. The process can be utilized to form recesses where desired such as may be implemented for metal contact fill, metal gate fill, interconnect fill, or the like.

Environmentally green process and composition for cobalt wet etch

In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

Replacement gate MOSFET with a high performance gate electrode

A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

Overlapping contacts for semiconductor device

The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiOand SiNis not converted into a metal alloy silicide contact during the annealing step A. selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

Method and process for forming a self-aligned silicide contact

A contact metallurgy structure comprising a patterned dielectric layer having vias on a substrate; a silicide layer of cobalt and/or nickel located at the bottom of vias; a contact layer comprising Ti located in vias on top of the silicide layer; a diffusion layer located in vias and on top of the contact layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer comprises at least one member selected from the group consisting of copper, ruthenium, rhodium platinum, palladium, iridium, rhenium, tungsten, gold, silver and osmium and alloys thereof. When the metal fill layer comprises rhodium, the diffusion layer is not required. Optionally a seed layer for the metal fill layer can be employed.

Contact metallurgy structure

The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

Method for forming self-aligned metal silicide contacts

A method includes providing a substrate including a non-insulative, silicon-including region for silicidation, the substrate including one or more contaminants at a top surface thereof. A getter layer is deposited over the non-insulative, silicon-including region, the getter layer reacting with at least one of the one or more contaminants in the non-insulative, silicon-including region at approximately room temperature. The getter layer is removed, and siliciding of the non-insulative, silicon-including region is performed.

Surface cleaning using sacrificial getter layer

A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

Method of forming electrodeposited contacts

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Putnam Valley, NY, United States of America

Randolph F Knarr