Micron Technology Incorporated

Applied Materials, Inc.

Micron Semiconductor, Inc.

Sandisk 3d LLC

Other

Micron Display Technology, Inc.

Randhir P Thakur

Scott Jeffrey DeBoer

Gurtej S Sandhu

Husam N Al-Shareef

Nitin K Ingle

Er-Xuan Ping

Fernando N Gonzalez

Shankar Venkataraman

Annette L Martin

Klaus Florian Schuegraf

Dmitry Lubomirsky

Anchuan Wang

Michael L Nuttall

Zhijun Chen

Xinglong Chen

Zihui Li

Ching-Mei Hsu

Jiayin Huang

Hiroshi Hamana

Scott J Deboer

Dave Chapek

Kirk D Prall

Alan R Reinberg

Vinod Robert Purayath

Daniel Gealy

John K Zahurak

J Brett Rolfson

Ronald Allen Weimer

Zhiqiang (Jeff) Wu

F Daniel Gealy

David L Chapek

James Pan

Brett Rolfson

Howard E Rhodes

Tyler A Lowrey

Charles H Dennison

Yongjun Jeff Hu

Pai-Hung Pan

Aftab A Ahmad

Lyle D Breiner

Kaushal Kishore Singh

Robert James Burke

Sundar Ramamurthy

Richard C Hawthorne

Er-Xang Ping

Klaus F Schugraf

Roy E Scheuerlein

John T Moore

Li Li

Ravi T Iyer

David K Carlson

Richard H Lane

Garry Anthony Mercaldi

Andreas G Hegedus

Russell C Zahorik

Satheesh Kuppurao

Ralph E Kauffman

Paul A Paduano

Zhigiang (Jeff) Wu

Manish Hemkar

Avishai Kepten

Michael Sendler

Christopher Alan Moore

Trung Tri Doan

Kunal R Parekh

Pierre C Fazan

Gordon A Haller

Philip Allan Kraus

Kevin G Donohoe

Dan Maydan

Xianmin Tang

Christopher Sean Olsen

Mark Fischer

Dean C Jennings

Yauh-Ching Liu

Pravin K Narwankar

Viju K Mathews

Dan Gealy

Lakshmanan Karuppiah

Shreyas Kher

Charles L Turner

Sairaju Tallavarjula

Shankar Muthukrishnan

James Beck

Mayur Trivedi

Sushil Padiyar

Michael J Prucha

Brian Benard

Klaus Scheugraf

Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

Processing systems and methods for halide scavenging

Embodiments described herein generally relate to methods for forming silicide materials. Silicide materials formed according to the embodiments described herein may be utilized as contact and/or interconnect structures and may provide advantages over conventional silicide formation methods. In one embodiment, a one or more transition metal and aluminum layers may be deposited on a silicon containing substrate and a transition metal layer may be deposited on the one or more transition metal and aluminum layers. An annealing process may be performed to form a metal silicide material.

Methods for forming low resistivity interconnects

Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called '2-d flat cell' flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.

Integrated bit-line airgap formation and gate stack post clean

In some embodiments, an electronic device processing system is provided that includes a processing tool having a first subsystem configured to carry out a first subset of processes on a substrate having pattern features, the first subsystem including a first conformal deposition chamber and a first etch chamber. The processing tool includes a second subsystem coupled to the first subsystem and configured to carry out a second subset of processes on the substrate, the second subsystem including a second conformal deposition chamber and a second etch chamber. The processing tool is configured to employ the first and second subsystems to perform pitch division on the substrate within the processing tool so as to form a reduced-pitch pattern on the substrate. Numerous other embodiments are provided.

Semiconductor device processing tools and methods for patterning substrates

Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods include recessing silicon oxide dielectric gapfill to expose vertical sidewalls of polysilicon floating gates. The exposed vertical sidewalls are then isotropically etched to evenly thin the polysilicon floating gates on the same substrate processing mainframe. Both recessing silicon oxide and isotropically etching polysilicon use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. An inter-poly dielectric may then be conformally deposited either on the same mainframe or outside the mainframe.

Integrated oxide recess and floating gate fin trimming

Methods of etching back an oxide-nitride-oxide (ONO) layer of a 3-d flash memory cell without breaking vacuum are described. The methods include recessing the two outer silicon oxide dielectric layers to expose the flanks of the thin silicon nitride layer. The silicon nitride layer is then etched back from all exposed sides to hasten the process on the same substrate processing mainframe. Both etching back the silicon oxide and etching back the silicon nitride use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. The process may also be reversed such that the silicon nitride is etched back first.

Integrated oxide and nitride recess for better channel contact in 3D architectures

Methods are described for forming 'air gaps' between adjacent copper lines on patterned substrates. The air gaps may be located between copper lines on the same layer. A sacrificial patterned dielectric layer is used as a template to form a layer of copper by physical vapor deposition in a substrate processing system (i.e. a mainframe). Without breaking vacuum, the copper is redistributed into the gaps with a copper reflow process. Dielectric material from the template is removed, again in the same mainframe, using a remote fluorine etch process leaving the gapfill copper as the structural material. A conformal capping layer (such as silicon carbon nitride) is then deposited (e.g. by ALD) to seal the patterned substrate before removing the patterned substrate from the mainframe.

Metal air gap

Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-many storage sub-system memory device including write-many memory cells, a write-once storage sub-system memory device including write-once memory cells, and a page-based interface that is adapted to read and write the write-once and write-many storage sub-system memory devices. Numerous other aspects are provided.

Storage sub-system for a computer comprising write-once memory devices and write-many memory devices and related method

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Boise, ID, United States of America

Randhir P Thakur