Atmel Corporation

Randall Wayne Melton

Kerry D Maletsky

Brad Phillip Garner

In an embodiment, multi-precision numbers A and B are accessed from a storage device (e.g., a memory array), where A is a dividend and B is a divisor. A multi-precision division operation is iteratively performed on the numbers A and B including: performing a multi-precision subtraction operation on A and B during a first iteration of the multi-precision division operation; performing a multi-precision addition operation on A and B during a second iteration of the multi-precision division operation as a result of a determination that a final borrow occurred during the subtraction operation; and performing a multi-precision addition operation on A and B after a final iteration of the multi-precision division operation.

Optimized multi-precision division

A data security system that includes a first memory device to store message data to be secured, a second memory device to store microcode including an instruction set defining a cryptographic algorithm for use in securing the message data, and a processing unit to execute the microcode to implement the cryptographic algorithm.

Data security system

A counter is efficiently implemented in non-volatile memory by using two binary counters and selectively using one or the other as a current counter. Writes to the binary counters are minimized by using two linear counters and using the state of the binary counters to determine which binary counter contains the current count. Write operations can be performed to the 'not current' binary counter with the final write operation being to the linear counters. The linear counter write operations can be in program-only mode so that a power failure will not result in a loss of counts.

Non-volatile memory counter

An integrated circuit (IC) security apparatus with complementary security traces and a method for producing such an apparatus is disclosed. The security apparatus comprises a pattern generator, and a plurality of security traces. The arrangement of security trace pairs are such that the second trace is arranged substantially parallel to the first trace. The pattern generator produces two signals, a second signal, which is applied to the second trace, is substantially complimentary to the first security trace. The timing and amplitude of the second (complimentary) signal is developed such that any net induced currents are substantially nulled. One or more of the signals is received from the signal generator and compared to the same signal after it is conducted through a security trace. The results are analyzed to determine if the security of the IC has been breached.

Security method for data protection

Multiple devices coupled to a communication system share a common or same configuration address. For each configuration address, multiple configuration registers are defined by the communication system. Each device sharing a common configuration address responds to a communication command after the configuration address and the configuration register have been identified as being assigned to or associated with the specific device having the assigned configuration address and configuration register.

LPC configuration sharing method

In an embedded system with a processor and an EEPROM that provides an EEPROM BUSY signal if the EEPROM is in a write mode, a block-before-write subroutine is used to hold the processor before a write operation to the EEPROM. A detector circuit finds read functions that are to be mapped into the EEPROM address space and suspends code execution if an EEPROM BUSY bit is asserted and the EEPROM is the read target. Code execution by the processor and processor access to memories other than the EEPROM is permitted while the EEPROM is being written. If any access is made by the processor to the EEPROM while the EEPROM BUSY bit is asserted, the processor enters a WAIT state to temporarily suspends execution of program code.

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Olney, MD, United States of America

Randall Wayne Melton