Texas Instruments Corporation

Randall W Pak

Brian Keith Kirkpatrick

Jinhan Choi

Clint Montgomery

Brian M Trentman

A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first metal including layer on the gate dielectric layer. A polysilicon or amorphous silicon layer is formed on the first metal including layer to form an intermediate gate electrode stack. A masking pattern is formed on the intermediate gate electrode stack. The polysilicon or amorphous silicon layer is dry etched using the masking pattern to define a patterned intermediate gate electrode stack over the NMOS or PMOS regions, wherein the dry etching stops on a portion of the first metal comprising layer. The masking pattern is removed using a first post etch clean for stripping the masking pattern. A multi-step solution cleaning sequence is used after the removing step and includes a first wet clean including sulfuric acid and a fluoride, and a second wet clean after the first wet clean including a fluoride. Fabrication of the IC is then completed.

Post metal gate VT adjust etch clean

The present invention provides a process of manufacturing a semiconductor device that comprises a process of manufacturing a semiconductor device that includes plasma etchingthrough a patterned hardmask layerlocated over a semiconductor substratewherein the plasma etching forms a modified layeron the hardmask layer, and removing at least a substantial portion of the modified layerby exposing the modified layerto a post plasma clean process.

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Plano, TX, United States of America

Randall W Pak