Cadence Design Systems, Inc.

Randall Scott Lawson

Karl Brice Orndorff

Arnold Michael Morris

Daphne Carolyn D'zurko

James Warren Jr. Barkell

Richard Hugh Pilsbury

Ken Wadland

Sean Bergan

Richard Allen Woodward, Jr

Richard Woodward

Brett Allen Neal

Jelena Radumilo-Franklin

Charles Winston Grant

Greg Horlick

Paul S Musto

Steve Russo

William Schilp

Walter M Katz

Frank X Farmar

Glendine Kingsbury

Utpal Bhattacharyya

Joseph Dexter Smedley

Edward Brian Acheson

Gregory M Horlick

Kota Sujan Reddy

Davis Tsai

Keith Woodward

Jia Wu

Donald Keith Morgan

Keith Woodword

Amit Kumar Sharma

Regis R Colwell

Robert Roesler

Edmund J Hickey

Mahmoodreza Jahanseirroodsari

Jelena Radumilo-Frankilin

Alan G Strelzoff

David Tsai

Rahil Rajesh Kothari

Wiley Gillmor

Joe Smedley

James Warren Jr Barkell

The present disclosure relates to a system and method for use in an electronic circuit design. Embodiments may include receiving, using a processor, one or more DFM rules files from at least one PCB fabricator and importing the one or more DFM rules files to a DFM rule aggregator database. Embodiments may also include grouping one or more rules associated with the one or more DFM rules files using an automated or manual operation. Embodiments may further include performing automatic or manual rule aggregation on the grouped rules based upon, at least in part, rules aggregation information including a DFM template file.

System and method for consolidating and applying manufacturing constraints

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using a processor, an electronic design and providing, at a graphical user interface, an option to change an object associated with the electronic design. Embodiments may further include identifying a damage area associated with the electronic design, the damage area including an object therein. Embodiments may also include generating a polygon for the damage area and caching one or more voids located outside of the damage area. Embodiments may further include performing a cut and stamp operation on a portion of the electronic design associated with the damage area and populating, at the graphical user interface, a repaired damage area.

System and method for updating shapes associated with an electronic design

The present disclosure relates to a system and method for use in an electronic circuit design. Embodiments may include an electronic computer aided design ('CAD') system configured to receive one or more design rules and to receive one or more manufacturing rules. The CAD system may be further configured to analyze design database objects from the electronic design with respect to the manufacturing rules. The CAD system may generate a manufacturing output file, based upon, at least in part, the analyzing. Embodiments may also include a signoff computer aided manufacturing ('CAM') station configured to receive the manufacturing output file. The CAM station may be configured to attempt to validate the manufacturing output file.

Process for analyzing printed circuit board and packaging manufacturing design rules

The present disclosure relates to a method for routing in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, the electronic circuit design having a plurality of terminal pads associated therewith. Embodiments may further include generating a change in at least one of a size or an existence of at least one of the plurality of terminal pads. Embodiments may also include routing a portion of the electronic design based upon, at least in part, the generated change.

Routing process including dynamically changing pad sizes

The present disclosure relates to a computer-implemented method for routing in an electronic circuit design. The method may include assigning a plurality of rats interconnecting one or more terminals associated with a layout of the electronic circuit design to a bundle. The method may further include sequencing the plurality of rats within the assigned bundle to generate a defined sequence of rats within the assigned bundle. The method may also include routing the plurality of rats between the one or more terminals, based upon, at least in part, the defined sequence.

System and method for electronic design routing between terminals

The present disclosure relates to a method for routing in an electronic circuit design. The method may include assigning a plurality of rats interconnecting one or more terminals associated with a layout of the electronic circuit design to a bundle. The method may also include generating an independent breakout of the plurality of rats from a source end and a target end of the bundle. The method may further include sequencing the plurality of rats within the assigned bundle to generate a defined sequence of rats within the assigned bundle based upon, at least in part, the source end of the bundle. The method may additionally include generating a costed sequence breakout at the target end of the bundle, based upon, at least in part, a costed sequence analysis. The method may also include determining if the costed sequence breakout meets at least one criteria associated with the electronic design.

Routing process

A method, computer program product and apparatus for utilizing simulated locking prior to starting concurrent execution are disclosed. The results of this simulated locking are used to define a canonical ordering which controls the order of execution and the degree of parallelism that can be used.

Deterministic, parallel execution with overlapping regions

A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful routing of all needed terminals, an at least partially routed circuit design may be output.

Method and system for routing optimally between terminals through intermediate vias in a circuit design

In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (TOPO) transformation engine, and a detail geometric (DETAIL) engine, and a command and control module (CCM) coupled together. The RDM reads and write data with a design database as well as reading one or more object oriented design constraints. Each of the routing engines have at least one action to operate on the design database to improve compliance of the circuit to a constraint. The CCM controls the overall routing process of the nets in the circuit and includes at least one director to invoke at least one of the routing engines to achieve compliance with one or more constraints.

Systems for automatic circuit routing with object oriented constraints

A method and system for auto-routing wiring within a PCB. In some embodiment, a first broad region within a first layer and a counterpart first broad region within a second layer are defined. The counterpart regions define a first broad via location. In some embodiments, the first and second broad via locations of the first and second layers can then be subdivided into a plurality of triangular regions. The triangular regions on the first and second layers can then be compared to more accurately locate an appropriate via location.

Method and mechanism for implementing PCB routing

Techniques that can improve the efficiency of routing where connections are subject to elongation constraints. The design can be optimized by estimating elongation needed to meet constraints after an initial routing solution has been generated, but before elongation is actually applied to detailed paths. Paths can be re-routed at this earlier stage if it is determined that too much elongation, or too much elongation in crowded areas, will need to be added after the detail routing stage.

Global constraint optimization

A routing method for a multilayer circuit design layout that has a set of possible preferred local routing directions and a default preferred routing direction for each layer. The method receives a set of user specified constraints on routing directions for particular regions of the design layout. The method tessellates the available routing space into separate tiles and automatically defines a preferred local routing direction for each tile based on the user specified constraints. The set of user specified constraints includes user designated flows, locked etches, 'etch keep-out' areas, user 'planned' data, etc. A routing method for a multilayer design layout that receives a first set of user specified preferred routing directions for particular regions of the multilayer design layout. The method tessellates the available routing space into separate tiles and automatically defines a second preferred local routing direction for each tile based on the user specified preferred routing directions.

Localized routing direction

Local constraints on placement of routing objects for direct connections between terminals in a circuit layout are determined from global constraints on the placement of the routing objects in a process referred to as global constraint budgeting. An autorouter finds paths in the layout to satisfy the local constraints and ignores the global constraints. The local constraints are updated before each routing pass to ensure that routes are completed on individual direct connections while also satisfying the global constraint.

Budgeting global constraints on local constraints in an autorouter

An approach is provided for selectively optimizing a circuit design to be physical implemented. The approach includes generating a circuit routing solution in accordance with a plurality of constraints for parametric resources of the circuit design, with the constraints being defined respectively by a plurality of corresponding constraint instances. Each constraint instance variably indicates an effective constraining limit and degree of consumption for at least one of the parametric resources. At least one of the constraints is selectively adjusted by a predetermined over-constraining amount, and the circuit routing solution is preliminarily modified by applying at least one routing action selected responsive to the constraint adjustment. An automatic evaluation is then made of the potential impact upon constraint compliance. The evaluation includes generating a relative cost measure for the preliminary modification of the circuit routing solution, based at least partially upon each of the constraint instances. Thereafter, the preliminary modification of said circuit routing solution is either discarded or accepted responsive to the evaluation. A number of these operations may be repeated in recursive manner, if appropriate for the given application.

Method and system for optimized circuit autorouting

Growing community of inventors

Seabrook, NH, United States of America

Randall Scott Lawson