International Business Machines Corporation

Randall Scott Jensen

William Paul Hovis

Edward T Gerchman

Mark C Gildea

Warren Edward Maule

Joseph Allen Kirscht

Michael T Peets

Andrew Henry Wottreng

Scott Douglas Clark

Paul William Rudrud

Thomas James Osten

William Hugh Cochran

Mark G Veldhuizen

A method and apparatus are provided for implementing a redundancy enhanced differential signal interface. A differential signaling I/O pair is coupled to a differential receiver interface. The differential receiver interface includes a pair of multiplexers coupled to a differential receiver. An error detecting mechanism is coupled to the differential receiver for detecting an error. When an error is detected, an interface operating speed is reduced. True and complement sides of a differential signaling I/O pair are alternately tested by first enabling a multiplexer control of one of the multiplexers, reading data, and checking for the error; then enabling a multiplexer control of the other multiplexer, reading data, and checking for the error. Responsive to detecting a failure of a true side or a complement side, the detected failed true side or complement side is set to a reference voltage and the reduced interface operating speed is maintained for continued operation.

Method and apparatus for implementing redundancy enhanced differential signal interface

A connector for attaching a printed circuit board to other apparatus is formed as a separate connector body with a plurality of pins projecting from one end surface that are attached to the printed circuit board by being secured in vias through the board and a threaded opening at the end surface opposite the one end surface from which the pins project. When a bolt is received in the connector threaded opening and drawn tight to secure the printed circuit board to other apparatus, the stresses and material deformation induced by the securing bolt are isolated from the printed circuit board. Further, the attachment of the pins to the printed circuit board rather than the use of screws extending through holes in the circuit board reduces the size of 'keep out' zones that must be avoided by the wiring paths on each wiring surface of the printed circuit board through which mounting holes extend. Fabrication of the connector and assembly of the connector to the printed circuit board are facilitated by providing a pair of parallel side surfaces on the connector body which can be gripped by a tool. The connector can also be used to electrically insulate or provide a current path by the selection of the polymer that forms the connector body portion.

Pin mounted circuit board retainer

A memory controller, upon detecting an interval of inactivity (that is, no read or write access from a processor or I/O devices with respect to main storage or memory SDRAMs) halts external refresh commands from the processor, and initiates STR mode in main storage to preserve data contents in the memory SDRAMs and to save energy. Then, upon detecting a read or write operation, the memory controller signals main storage to exit STR mode.

System and method for memory self-timed refresh for reduced power consumption

A storage controller, upon detecting an interval of storage inactivity, inhibits external storage refresh commands and places the storage in self timed refresh (STR) mode. Upon detecting storage activity while storage is in STR mode, the controller terminates STR mode in storage. Upon detecting a scrub request while storage is in STR mode, the controller terminates STR mode in the storage and thereafter services the scrub request. Upon completing execution of the scrub request, the controller returns storage to STR mode.

System and method for memory scrub during self timed refresh

A memory arrangement, where a memory control logic, which drives a memory array, is maintained in a volatile power domain, and clock redrive circuitry, address control redrive circuitry, data transceiver, and the memory array itself are all maintained in a non-volatile power domain, in order to increase the effective life time of a battery backup system. The memory arrangement includes buffering circuitry to prevent leakage currents, and the appropriate control of nets between the memory control logic and the memory array, in order to avoid additional sources of leakage current and bus driver contentions.

Growing community of inventors

Rochester, MN, United States of America

Randall Scott Jensen