International Business Machines Corporation

Randall Ray Heisch

Venkat Rajeev Indukuru

Philip Lee Vitale

William A Bostic

Jesse L Sathre

Allan E Johnson

Guy L Guthrie

Bret Ronald Olszewski

Steven Wayne White

Robert J Blainey

Roch Georges Archambault

Aaron Christoph Sawdey

Paul Jerome Kilpatrick

John Michael Attinella

Sohel Riazuddin Saiyed

Allen E Johnson

Yaoging Gao

Mechanisms are provided for a graphical user interface tool for system-wide topology and performance monitoring with per-partition views. A graphical user interface application presents a consolidated view of physical and logical information based on the received performance data. The mechanisms provide real-time performance and utilization information in a visual format relative to the physical components in a topographical layout. The user may drill down to lower levels to view more detailed performance and utilization information.

System-wide topology and performance monitoring GUI tool with per-partition views

A prefetch optimizer tool for an information handling system (IHS) may improve effective memory access time by controlling both hardware prefetch operations and software prefetch operations. The prefetch optimizer tool selectively disables prefetch instructions in an instruction sequence of interest within an application. The tool measures execution times of the instruction sequence of interest when different prefetch instructions are disabled. The tool may hold hardware prefetch depth constant while cycling through disabling different prefetch instructions and taking corresponding execution time measurements. Alternatively, for each disabled prefetch instruction in the instruction sequence of interest, the tool may cycle through different hardware prefetch depths and take corresponding execution time measurements at each hardware prefetch depth. The tool selects a combination of hardware prefetch depth and prefetch instruction disablement that may improve the execution time in comparison with a baseline execution time.

Method of prefetch optimizing by measuring execution time of instruction sequence cycling through each selectable hardware prefetch depth and cycling through disabling each software prefetch instruction

Prefetch optimizer measuring execution time of instruction sequence cycling through each selectable hardware prefetch depth and cycling through disabling each software prefetch instruction of an instruction sequence of interest

Systems, methods and computer program products may provide monitoring of software performance on a computer. A method of monitoring software performance in a computer may include marking at least one of a load request and a store request, the marked request including an effective instruction address and an effective data address, recording the effective instruction and data addresses in a processor core and sending the marked request to a memory subsystem. The method may also include receiving a fabric response for the marked request, recording the fabric response in the core and tying the effective instruction and data addresses and the fabric response together in a sample.

Monitoring software performance

Methods, systems, and products for determining performance of a software entity running on a data processing system. The method comprises allowing extended execution of the software entity without monitoring code. The method also comprises intermittently sampling behavior data for the software entity. Intermittently sampling behavior data may be carried out by injecting monitoring code into the software entity to instrument the software entity, collecting behavior data by utilizing the monitoring code, and removing the monitoring code. The method also comprises repeatedly performing iterations of the allowing and sampling steps until collected behavior data is sufficient for diagnosing performance of the software entity. The method may further comprise analyzing the collected behavior data to diagnose performance of the software entity.

Determining performance of a software entity

Mechanisms for providing a floating display without moving electronics is provided. The mechanisms include a stationary array of light emitting elements and a moving reflective element. As the reflective element rotates, oscillates, or otherwise moves in a path relative to the array of light emitting elements, a controller controls the illumination, i.e. the pulsing on and off, of the light emitting elements based on a location of the reflective element so as to achieve a desired image, alphanumeric message, graphical display, animated display, or the like. The reflective element may be a reflective sphere having a reflective exterior surface. In this way, the electronics used to generate the floating display are kept stationary while the reflective element is moved along a path of motion to generate the floating image. This reduces the complexity and cost of the electronics needed to generate a floating image.

Providing a floating alphanumeric/graphical display without moving electronics

An electronics support apparatus for rotating electronics is provided that eliminates the need for electrical contact brushes and/or reduces the number of inductive power coupling coil pairs required to provide power to the rotating electronics. With the apparatus, a single inductive power coupling coil pair is utilized in which the coils are oriented at approximately 90 degrees, i.e. at a right angle, to each other, e.g., the 'outer' coil (secondary transformer coil) is oriented approximately 90 degrees to the 'inner' coil (primary transformer coil). A transformer core, or &#x201c;elbow core,&#x201d; having an approximately 90 degree bend is provided for coupling the magnetic energy of the primary transformer coil with the secondary transformer coil, thus imparting or coupling energy simultaneously through 2 axes of motion.

Single coil pair, multiple axis inductive power coupling apparatus and method

An light-emitting diode (LED) meter capable of analog presentations is disclosed. The LED meter includes an LED and a reflective object. The reflective object is capable of reflecting light emitted from the LED. The reflective object is also capable of being moved to and for along a path. The LED meter also includes means for selectively enabling the LED to emit light continuously for a duration that is proportional to a magnitude of measurement.

Apparatus for implementing a light-emitting diode meter

A method, apparatus, system, and signal-bearing medium that, in an embodiment, retrieve event data from a processor for sampling intervals, where the sampling intervals are evenly distributed, but the control points at which the event data is retrieved are unevenly distributed. The processor executes instructions for logical partitions, and the event data is associated with events that are detected by the processor during the sampling intervals. In response to an interrupt received from the processor at the control point, a determination is made whether the sample point has been reached. If the sample point has been reached, the event data is retrieved from the processor and an event counter is reset to a value that is calculated to cause the processor to include an identical number of the events in the sampling intervals. The value is calculated based on the event counter at the time control point, the event counter at a time of the sample point, and the number of events in the sampling interval. In this way, an even distribution of event data may be collected when the processor is allocated to multiple partitions in a logically-partitioned system.

Retrieving event data for logical partitions

A method and system for reducing or avoiding store misses with a data cache block zero (DCBZ) instruction in cooperation with the underlying hardware load stream prefetching support for helping to increase effective aggregate bandwith. The method identifies and classifies unique streams in a loop based on dependency and reuse analysis, and performs loop transformations, such as node splitting, loop distribution or stream unrolling to get the proper number of streams. Static prediction and run-time profile information are used to guide loop and stream selection. Compile-time loop cost analysis and run-time check code and versioning are used to determine the number of cache lines ahead of each reference for data cache line zeroing and to tolerate required data alignment relative to data cache lines.

Aggregate bandwidth through management using insertion of reset instructions for cache-to-cache data transfer

A system, method, and computer program product are disclosed for reducing overhead associated with software lock monitoring in a multiple-processor data processing system having a memory that is shared among the multiple processors. Multiple memory locations in the shared-memory are associated with one of multiple locks. Overhead is reduced by generating a trace hook only in response to activity associated with lock misses.

System, method, and computer program product for reducing overhead associated with software lock monitoring

A system and method are provided that allows the results of an instruction trace mechanism to globally restructure the instructions. The process reorders the instructions in an executable program, using an actual execution profile (or instruction address trace) for a selected workload, to improve utilization of the existing hardware architecture. The reordering of instructions is implemented at a global level (i.e., independent of procedure or other structural boundaries which maximizes speedup) running on various hardware platforms and adds the ability to preserve correctness and debuggability for reordered executables. An unconditional branch instruction is added at the memory locations where reordered instructions previously were stored. When a dynamic branch occurs, the program will attempt to access the instruction at the original address and the unconditional branch directs the program to the reordered location of the instruction and program integrity is maintained.

Method and system for reordering the instructions of a computer program

A microprocessor performance monitor and instruction address break point facility are interconnected to provide finer granularity and performance monitoring. The microprocessor is initialized to collect processor statistics preselected prior to performance monitoring. Application start and stop instruction breakpoint addresses are preselected from a software program bounding instructions for which such statistics are desired. An exception handler is installed for instruction address breakpoints (IAB), enabling and disabling the performance monitor and stop addresses, respectively. The IAB register is then initalized to the start address, and the statistics counters are cleared. Upon starting the application, when the application start address instruction is executed, the breakpoint handler obtains control and enables the performance monitor counters, which count the desired statistics after returning from the breakpoint handler. Before returning, the handler sets the IAB register to the stop address. When the application stop address is encountered, the breakpoint handler disables the performance monitor counters, and rearms the start address in the IAB register. The performance monitor counters are then read to determine the desired statistics for the specific sequence of code within the boundaries of the start and stop addresses in the application.

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Georgetown, TX, United States of America

Randall Ray Heisch