Apple Inc.

Randall R Rauwendaal

Jim Chen Chou

Moinul H Khan

Hao Pan

Arthur Yasheng Zhang

Nicolas P Bonnier

Tobias Eble

Ralph Clay Taylor

Justin A Hensley

Jonathan M Redshaw

Karl D Mann

Cody J White

Ye Cong

In one implementation, a method includes receiving a warped image representing simulated reality (SR) content (e.g., to be displayed in a display space), the warped image having a plurality of pixels at respective locations uniformly spaced in a grid pattern in a warped space, wherein the plurality of pixels are respectively associated with a plurality of respective pixel values and a plurality of respective scaling factors indicating a plurality of respective resolutions at a plurality of respective locations of the SR content (e.g., in the display space). The method includes processing the warped image in the warped space based on the plurality of respective scaling factors to generate a processed warped image and transmitting the processed warped image.

Dynamic foveated pipeline

Techniques are disclosed relating to rendering graphics objects. In some embodiments, a graphics unit is configured to transform graphics objects from a virtual space into a second space according to different transformation parameters for different portions of the second space. This may result in sampling different portions of the virtual space at different sample rates, which may reduce the number of samples required in various stages of the rendering process. In the disclosed techniques, transformation may occur prior to rasterization and shading, which may further reduce computation and power consumption in a graphics unit, improve image quality as displayed to a user, and/or reduce bandwidth usage or latency of video content on a network. In some embodiments, a transformed image may be viewed through a distortion-compensating lens or resampled prior to display.

Multi-space rendering with configurable transformation parameters

Techniques are disclosed relating to tessellation of graphics patches. In some embodiments, tessellation circuitry is configured to divide patches into sub-patches for further independent processing. This may improve performance and/or reduce power consumption, in various embodiments. In some embodiments, the tessellation circuitry is first configured to divide an inner portion of the patch into a predetermined number of quad-shaped regions (e.g., three for triangle patches and four for quad patches). In some embodiments, the tessellation circuitry is configured to divide one or more of the regions into a number of sub-patches such that a value indicative of a number of vertices in each sub-patch is below a threshold value.

Sub-patch techniques for graphics tessellation

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San Jose, CA, United States of America

Randall R Rauwendaal