Western Digital Corporation

Pictos Technologies, Inc.

Other

Conexant Systems, Inc.

Ess Technology, Inc.

Rockwell Science Center, Inc.

Spacefab.us, Inc.

Edgestream, Inc.

Randall M Chung

Magued M Bishay

Sarit Neter

William H Ambrosius, Iii

Ian Olsen

James K Dawson

David Escobar

Mike Fukatsu

Edward Andrew Jakl

Gregory Urban

Bradley S Masters

Sivagnanam Parthasarathy

Richard Arthur Mann

Shaun Astarabadi

Joshua I Pine

Maged Bishay

Larry D Rossean

Robert L Mifflin

Ferry Gunawan

Dino D Trotta

Paul K Kim

Gregory A Urban

Michael Zelevinsky

Wei Feng

A modular beam amplifier for use in generating high power beams of particles in systems such as a spacecraft propulsion engine, comprising a distributed DC power generator including a plurality of DC generator cells connected in series to each other and a plurality of power taps at different points between the DC generator cells, an ion injector producing a particle beam and a plurality of amplifier modules in series with each other and coaxial with the particle beam. Each amplifier module in the plurality of amplifier modules includes a focus lens and a plurality of annular amplifier plates. Each amplifier plate pairs with and connects to a power tap. The plurality of DC generator cells is physically arranged in a serpentine arrangement of connected rows to minimize the physical length of the distributed DC power generator.

Modular beam amplifier

The invention is a technique and apparatus for re-assembling transmitted portions of files or sub-files (), into a viewable file (). The transmitting device passes the information regarding the file dividing process to the receiver so that the sub-files can be assembled () or stitched () together properly. The media player () in the receiver uses the attached instructions to assemble the sub-files into one whole piece for viewing.

Re-assembly of streaming files from separate connections

A communication system including an infrared receiver that receives optical infrared signals. The infrared receiver utilizes an array of photo-sensors for detecting optical infrared signals within a solid angle. Each photo-sensor, however, detects optical infrared signals in only a predetermined portion of the solid angle. On detecting optical infrared signals, each photo-sensor converts and forwards a corresponding electrical signal to a filter circuit that selectively determines whether the signal meets a predetermined criteria such as a frequency threshold. The filter circuit or other processing circuitry is thereby able to identify photo-sensor(s) providing an optimal infrared communication link. The infrared receiver may include an optical system comprising a lens assembly that directs the optical infrared signals towards the array of photo-sensors. In one embodiment, the lens assembly employs a diffused lens having an imperfect focus to facilitate the detection of optical infrared signals emanating from transmitters that have a relatively small solid angle.

Infrared communication system utilizing receiver with multiple photo-sensors

A data interface for CMOS imagers is disclosed that can be either a single-ended interface or a differential interface. The single-ended interface provides compatibility with many existing external devices. Further providing a differential interface allows a lower noise and a lower power interface for external devices that can support a differential signal. The combined single-ended and differential signal interface does not increase the number of pins required for a single-ended only interface. The data transfer width is set to the word width, which allows a fixed timing relationship between the clock edge and data transfer in both single-ended and differential modes. In single-ended mode, the data is transferred once per clock, but in the differential mode, the data is transferred twice per clock, once on each clock edge. This fixed timing relationship eliminates the need for and cost of explicit bit synchronization.

Combined single-ended and differential signaling interface

The present invention discloses an electronic camera which processes the exposure of light by means of an imaging surface comprising a plurality of active pixel sensor circuits. Each pixel sensor circuit produces a small current inversely proportional to the amount of light that has fallen on a photodiode within the pixel sensor circuit. The individual currents produced by the active pixel sensor circuits are aggregated onto one or more current collection busses and operatively channeled to an operational amplifier assigned to a given bus. If a single operational amplifier is used, its output voltage is compared to a preset voltage level. When the voltage level decays to a preset level, a control signal is signaled. The control signal may be used to terminate further light exposure through traditional means such as triggering a &ldquo;snubber&rdquo; tube which immediately discharges the flash tube storage capacitor or turning off an IGBT high power transistor controlling the current through the flash tube, or, it may trigger an electronic shutter which prevents further photographic development of the imaging surface. Through the use of multiple operational amplifiers, different sectors of the imaging surface can be &ldquo;weighted,&rdquo; thereby giving greater effect to the light falling on select portions of the imaging surface.

Real time camera exposure control

A semiconductor component that receives incoming light includes an integrated circuit, a package and an optics unit. The optics unit may provide a pathway, either generally or selectively, for the incoming light to the photodetector circuitry of the integrated circuit and may modify the incoming light, as well. The optics unit may be either electrically active or passive. When active, the optics unit is coupled to the integrated circuit with a conductor. The optics unit may also include a liquid crystal device, a beamsplitter assembly, a lensing assembly or other filters, and/or apertures. The liquid crystal device can act as a shutter or a display and the optics unit may be a single module or a plurality of modules. The integrated circuit may also include shutter drive circuitry and image processing circuitry.

Integrated circuit optics assembly unit

The invention is an imaging device having a high fill factor. The high fill factor is achieved by constructing the light sensors in a vertical fashion in the imaging device. The control circuitry of the light sensor is then contained inside the integrated circuit chip, rather than taking up area that could otherwise be used for light collection. The majority of the area on the surface of the IC chip is made up of light sensing elements, since the control circuitry is embedded in the IC chip. The control circuitry is connected to the light sensing devices through vias in the IC chip. The control circuitry of the chip is mainly contained within the die, rather than on it.

Light sensing system with high pixel fill factor

A camera system employs an electronic imager such as a Charged Couple Device (CCD) or a Complementary Metal Oxide Semiconductor (CMOS) array that captures a first portion of light and reflects a second portion of light reflected from a target subject. The light reflected by the electronic imager may be reflected towards film media or a color filter, for example. The electronic imager may include an integrated circuit, or a dielectric reflecting coating that acts to partially reflect incoming light reflected from the target subject. A display, such as an LCD (Liquid Crystal Display), may be utilized to determine which images are desirable or to identify which films to develop. Film writing circuitry that allows various types of information to be written may be utilized. The camera system further features an electronic imager shutter, and a film shutter for shuttering purposes. The film shutter can provide exposure control. The camera system additionally features a processing or control system that selectively controls using the electronic imager or the film media or both simultaneously. The camera system may also have a beamsplitter such as a prism, mirror or optical coating that transmits and reflects light from a subject towards an electronic imager and/or film media, respectively. In addition, the camera system can download digital images to a computer via interface circuitry.

Camera utilizing film and reflective imager

An imager reduces lighting induced flicker by setting its pixel integration time to an integral multiple of the periods between peak intensity of the lighting. In one implementation, flicker is reduced in a 30 Hz frame rate camera capturing an image lighted with 50 Hz lighting by setting the integration time to approximately 10 ms, the period between lighting intensity peaks.

Image flicker reduction with fluorescent lighting

A lid for protecting and covering an integrated circuit provided in a chip-on-board package is disclosed. The lid has a wall surrounding the integrated circuit, and a top cover covering the integrated circuit, with the wall and top cover provided in a single piece.

Single piece integrated package and optical lid

A system controller manages communication of data between a microprocessor, a memory and input/output controllers in a computer. A power management controller is operative upon occurrence of microprocessor inactivity indications to disable power to the microprocessor without disabling power to the input/output controllers. Operations of the power management controller is sequenced by a plurality of programmable registers, which are programmed by signals received either from a main data bus connected to the system controller, and other units, such as input/output controllers, a keyboard controller and from a memory, or a local data bus connected between at least one of the units and the system controller.

Integrated circuit chip core logic system controller with power saving

Disclosed is an improved logic circuit employing dynamic CMOS logic and having alternating logic employing first and second conductivity type transistors, respectively, separated by clocked inverters. The circuit employs a single clock signal to synchronize the dynamic logic operations of said logic gates and, along with a second, complement clock signal, said clocked inverters. Precharge transistors of each conductivity type are slowed slightly with respect to logic transistors, and the complement clock signal is delayed slightly with respect to the clock signal, thereby providing racefree logic operations. An implementation in a PLA is disclosed employing two logic planes for implementing arbitrary logic equations on input logic signals. The first logic plane and second logic plane are evaluated on separate phases of a complement clock signal and are separted by a clocked latch/inverter for providing correct logic evaluation between the logic planes.

CMOS circuit with racefree single clock dynamic logic

Disclosed is a programmable logic array employing dynamic CMOS logic and utilizing a single clock signal and its complement to synchronize said dynamic logic operations. The PLA disclosed employs two logic planes for implementing arbitrary logic equations on input logic signals. The first logic plane and second logic plane are evaluated on separate phases of a clock signal and its complement and are separated by a clocked latch/inverter for providing correct logic evaluation between the logic planes.

Programmable logic array with single clock dynamic logic

A digital data capture window extension circuit utilizing a matched pair of signal detection subcircuits that are activated during alternate cycles of a master read clock. The interleaved operation of the paired subcircuits permits each subcircuit to detect and process an incoming data signal, resulting in an effective overall processing rate twice that of prior art circuitry. The invention therefore permits the reading of data at a high rate using a system clock of the same frequency as the incoming data.

Data capture window extension circuit

An improved chip topography for a disk memory controller circuit is provided which includes electrical interface circuitry disposed around the periphery of the chip and forming an approximately quadrilateral framework surrounding the remainder of the circuitry, a read-only-memory (ROM) disposed in one corner of the interface framework; a microcontroller disposed adjacent to the ROM and along part of a first side of the interface framework; read data processing circuitry disposed adjacent to the microcontroller and within a second corner of the interface framework and along part of a second side thereof; error checking circuitry disposed adjacent to the read data processing circuitry and along part of the second side of the interface framework; the microcontroller also being disposed adjacent to the error checking circuitry and along part of the second side of the interface framework; write data processing circuitry disposed adjacent to the microcontroller along the second side of the interface boundary, within a third corner of the interface framework and along a part of a third side of the interface boundary; the microcontroller also being disposed adjacent to the write data processing circuitry and along the third side of the interface framework; input/output (I/O) buffer/latch circuitry disposed adjacent to the micro controller along the third side of the interface framework, which is also disposed within the fourth corner and along a part of a fourth side of the interface framework, the microcontroller also being disposed adjacent to and between the I/O buffer/latch circuitry and the ROM along the fourth side of the interface framework; and task registers disposed between the microcontroller and the I/O buffer/latch circuitry.

Growing community of inventors

Laguna Niguel, CA, United States of America

Randall M Chung