Northrop Grumman Systems Corporation

Microsoft Technology Licensing, LLC

Randall M Burnett

Quentin P Herr

Donald Lynn Miller

Anna Y Herr

Alexander Louis Braun

Harold Clifton Hearne, Iii

Ryan Edward Clarke

Timothy Chi-Chao Lee

Randal L Posey

Derek L Knee

Ofer Naaman

William Robert Reohr

Haitao O Dai

Eric C Gingrich

Mark B Ketchen

Dipankar Bhattacharya

Steven Brian Shauck

Jonathan D Egan

Henry Y Luo

Steven B Shauck

Harold Clifton Hearne

Edge-sensitive, state-based single flux quantum (SFQ) based circuitry and related methods convert return-to-zero (RZ) or non-return-to-zero (NRZ) encoded SFQ-pulse-based signals to bilevel NRZ phase signals that can subsequently be converted to bilevel voltage signals by an output amplifier (OA). The SFQ-based circuitry can be integrated with a current amplification stage of a driver that can be coupled to a stage of the OA. The SFQ-based circuitry can be made to be compatible with RQL-encoded input signals that can be either RZ or NRZ. The SFQ-based circuitry can thus be compatible with both wave-pipelined (WPL) and phase-mode (PML) RQL circuitry. Because the SFQ-based circuitry and related methods are edge-sensitive and state-based, they can function at system clock rates in excess of 1 GHz with reduced glitches and improved bit error rates as compared to other superconducting RZ-NRZ conversion circuitry and methods.

Circuits for converting SFQ-based RZ and NRZ signaling to bilevel voltage NRZ signaling

Superconducting output amplifiers having return to zero to non-return to zero converters are described. An example superconducting output amplifier (OA) includes a first superconducting OA stage having a first DC-SQUID and a second DC-SQUID arranged in parallel to the first DC-SQUID. The superconducting OA includes an input terminal for receiving a single flux quantum (SFQ) pulse train. The superconducting OA includes a first splitter configured to split a first set of SFQ pulses corresponding to the SFQ pulse train into a first return to zero (RZ) signal and a second RZ signal. The superconducting OA includes a first return to zero to non-return to zero (RZ-NRZ) converter configured to convert the first RZ signal into a first non-return to zero (NRZ) signal for driving the first DC-SQUID, and a second RZ-NRZ converter configured to convert the second RZ signal into a second NRZ signal for driving the second DC-SQUID.

Superconducting output amplifier having return to zero to non-return to zero converters

One example includes a pulse selector system. The pulse selector system includes an input Josephson transmission line (JTL) configured to propagate an input reciprocal quantum logic (RQL) pulse received at an input based on a bias signal. The RQL pulse includes a fluxon and an antifluxon. The system also includes an escape Josephson junction coupled to an output of the input JTL. The escape Josephson junction can be configured to pass a selected one of the fluxon and the antifluxon of the RQL pulse and to trigger in response to the other of the fluxon and the antifluxon of the RQL pulse to block the other of the fluxon and the antifluxon of the RQL pulse. The system further includes an output JTL configured to propagate the selected one of the fluxon and the antifluxon as a unipolar pulse to an output based on the bias signal.

Pulse selector system

Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a 'body' circuit that provides a single or multi-state sub-critical bias current to one or many independent 'tail' circuitries. Each &#x201c;tail&#x201d; has minimal effect on the &#x201c;body&#x201d; thereby preventing any interference or destruction to the state of the &#x201c;body&#x201d; circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

Superconducting non-destructive readout circuits

A bistable device allows supercurrent to flow when functioning in one regime, wherein magnetization directions of different magnetic layers are antiparallel, but restricts supercurrent when switched to function in a resistive regime, wherein the magnetization directions are parallel. In the first regime, the device acts as a Josephson junction, which allows it to be used in superconducting quantum interference devices (SQUIDs) and other circuits in which quantization of magnetic flux in a superconducting loop is desired. In the second, resistive regime, flux quantization is effectively eliminated in loops containing the device, and current is diverted to parallel superconducting components. The bistable device thereby acts as a superconducting switch, useful for a variety of circuit applications, including to steer current for memory or logic circuits, adjust logical circuit functionality at runtime, or to burn off stray flux during cooldown.

Superconducting switch

Superconducting logic arrays (SLAs) and field-programmable gate arrays (FPGAs) that are based on Josephson transmission lines (JTLs) accommodate reciprocal quantum logic (RQL) compliant binary input signals and provide RQL-compliant output signals that are evaluations of generalized logic functions. Each JTL-based superconducting FPGA (JTLBSFPGA) incorporates multiple JTL-based SLAs (JTLBSLAs) connected together. Each JTLBSLA includes an array of software-programmable and/or mask-programmed logic cells that output products of inputs and cell states, such that the JTLBSLAs output evaluations of sum-of-products functions. New JTLBSLA logic cells are described, including some that provide programmable cell states via magnetic Josephson junctions (MJJs). JTLBSFPGAs provide area efficiency and clock speed advantages over CMOS FPGAs. Unlike SLAs based on Josephson magnetic random access memory (JMRAM), JTLBSLAs do not require word line drivers, flux pumps, or sense amplifiers. Because JTLBSLAs and JTLBSFPGAs are RQL-compliant, they can also include RQL gates connected within or between them, without signal conversion circuitry.

JTL-based superconducting logic arrays and FPGAS

One example includes a superconducting bidirectional current driver. The current driver includes a first direction superconducting latch that is activated in response to a first activation signal to provide a first current path of an input current through a bidirectional current load in a first direction. The current driver also includes a second direction superconducting latch that is activated in response to a second activation signal to provide a second current path of the input current through the bidirectional current load in a second direction opposite the first direction.

Superconducting bi-directional current driver

One example includes a superconducting transmission line driver system. The system includes an input stage configured to receive an input pulse and an AC bias current source configured to provide an AC bias current. The system also includes an amplifier coupled to the input stage and configured to generate a plurality of sequential SFQ pulses based on the input pulse in response to the AC bias current. The system further includes a low-pass filter configured to filter the plurality of sequential SFQ pulses to generate an amplified output pulse that is output to a transmission line.

Superconducting transmission line driver system

Current-based superconductor memory cell and related systems and methods are provided. A method in a memory system, having at least one storage circuit and at least one read SQUID, includes applying bit-line current, via a read bit-line not including any Josephson transmission line (JTL) elements, to the at least one read SQUID. The method further includes applying word-line current, via a read word-line not including any JTL elements, to the at least one read SQUID. The method further includes using the at least one read SQUID reading a logic state of the memory cell based on data maintained in the storage circuit.

Memory system with signals on read lines not phase-aligned with Josephson transmission line (JTL) elements included in the write lines

JTL-based superconducting logic arrays and FPGAs

A memory system including an array of memory cells may include a set of word-lines, and a set of return word-lines coupled to the memory cells in the array of memory cells. The memory system may further include a set of bit-lines coupled to the memory cells. Each of the memory cells may include a memory storage element including a readout superconducting quantum interference device (SQUID), and a magnetic Josephson Junction (MJJ), and where the memory storage element may further include a differential transformer coupled in series with the MJJ such that in response to a bit-line current applied to at least one of the set of the bit-lines and a word-line current applied to at least one of the set of word-lines, the differential transformer is configured to induce a flux in the at least one readout SQUID.

Superconducting memory system with stacked drivers and differential transformers

One example includes a superconducting bidirectional current driver. The current driver includes a first direction superconducting latch that is activated in response to a first activation signal and a second direction superconducting latch that is activated in response to a second activation signal. The second direction superconducting latch is activated to provide a first current path of an input current through the first direction superconducting latch and through a bidirectional current load in a first direction. The first direction superconducting latch is activated to provide a second current path of the input current through the second direction superconducting latch and through the bidirectional current load in a second direction opposite the first direction.

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Randall M Burnett