Compaq Computer Corporation, Inc.

Western Digital Technologies, Inc.

Hewlett-packard Development Company, L.p.

Hgst Netherlands, B.v.

Compaq Information Technologies Group, L.p.

Randall L Hess

Mark A Piwonka

Drew S Johnson

Randy Roberson

Jeffrey D Kane

Berck Nash

Patrick R Cooper

Don R James, Jr

James Michael Reiser

Michael Walker

Susan Gaye Elkington

Louis B Hobson

Norman P Brown

David M Burckhartt

Jesse L Yandell

Mark D Moore

Kris B Stokes

Joseph F Freiman

Kevin W Mundt

David B Potter

Michael Stillwell

Armando Interiano

Chi Wai So

David R Wooten

Michael D Walker

Hung Q Le

Jeff W Wolford

Michael R Garrett

Christopher C Wanner

Gaines C Teague

David E Murray

Paul Dunn

Kurt C Lantz

Daniel B Reents

Jason Richard Huddleston

Mohammed Anwar Ramiz

Enhancements for managing quality of service in a multi-host Peripheral Component Interconnect Express (PCIe) switching environment involve a host system configured to maintain quality of service statistics corresponding to data interactions with a PCIe storage device available via a PCIe switch. The host system may further receive secondary quality of service statistics for one or more other host systems communicatively coupled to the PCIe device via the PCIe switch, and determine a maximum queue depth for the host system based on the quality of service statistics and the second quality of service statistics to maintain a quality of service for at least the host system.

Queue depth management for host systems accessing a peripheral component interconnect express (PCIe) device via a PCIe switch

Described herein are enhancements for managing multi-host Peripheral Component Interconnect Express (PCIe) switching. In one implementation, a PCIe switch coupled to a host processing system and PCIe slots may receive enumeration requests from the host processing system to identify available PCIe devices. In response to the enumeration requests, the PCIe switch may transfer responses to the host processing system indicating device identifier information for PCIe devices associated with the PCIe slots even if one or more of the PCIe devices is not currently installed.

Peripheral component interconnect express (PCIe) device enumeration via a PCIe switch

To provide enhanced operation of data storage devices and systems, various systems, apparatuses, methods, and software are provided herein. In a first example, a data storage device accumulates write data into a cache storage region prior to committing into an archive storage region and maintains a data structure that tracks the write data in the cache storage region. Responsive to receiving first write data into the cache storage region, the data storage device establishes first tracking elements in the data structure for the first write data in the cache storage region. Responsive to receiving second write data directed to storage locations overlapping the first write data, the data storage device accepts the second write data into the cache storage region and establishes second tracking elements in the data structure for the second write data in the cache storage region without modifying the first tracking elements.

Non-blocking caching for data storage drives

Described herein are enhancements for managing quality of service in a multi-host Peripheral Component Interconnect Express (PCIe) switching environment. In one implementation, a host system is configured to maintain quality of service statistics corresponding to data interactions with a PCIe storage device available via a PCIe switch. The host system may further receive secondary quality of service statistics for one or more other host systems communicatively coupled to the PCIe device via the PCIe switch, and determine a maximum queue depth for the host system based on the quality of service statistics and the second quality of service statistics to maintain a quality of service for the host systems.

Described herein are enhancements for managing multi-host Peripheral Component Interconnect Express (PCIe) switching. In one implementation, a system includes one or more PCIe devices and a PCIe switch configured to receive a first interrupt corresponding to a first interrupt vector from a PCIe device, wherein the first interrupt vector comprises at least a virtual address and a first data value. The switch is further configured to translate the first interrupt vector into a second interrupt vector, wherein the second interrupt vector comprises a second address and a second data value, and transfer a second interrupt using the second interrupt vector to a host of a plurality of hosts that corresponds to the second interrupt vector.

Multi-host peripheral component interconnect express (PCIe) switching based on interrupt vector from PCIe device

The present disclosure relates to systems and methods of an optimized data layout in an erasure coded storage system. The system may be realized as a deterministic layout of storage devices in an erasure coded storage system. The system implements a method for writing pieces of a data object across storage devices of a specified write set included an erasure coded storage subsystem. The system further implements a method for reading a subset of pieces of a data object from an active read subset of storage devices in a read set included in the erasure coded storage subsystem and restoring the data object from the subset of pieces. The system may further include operating an inactive read subset of storage devices in a read set in a low power mode.

Optimized data layout for object store system

A data storage array is presented that includes a plurality of storage drives each comprising storage media with a first storage region and a shingled magnetic recording (SMR) storage region. The data storage array includes a control system communicatively coupled to the storage drives and configured to receive a write operation over a host interface for storage of write data by the data storage array. Responsive to the write operation, the control system is configured to cache the write data in first storage regions of two or more of the storage drives prior to transfer of the write data into at least an SMR storage region of a storage drive associated with the write operation.

Enhanced redundant caching for shingled magnetic recording devices in data storage drive assemblies

To provide enhanced operation of data storage devices and systems, various systems, apparatuses, methods, and software are provided herein. In a first example, a data storage device is presented with storage media comprising a cache storage region and a shingled magnetic recording (SMR) storage region that is divided into burst zones. A storage control system receives write operations and accumulates write data in the cache storage region until a commit threshold condition. Responsively, the storage control system transfers the write data into a burst zone of the SMR storage region, and verifies the write data written into the burst zone once the burst transfer is complete. Responsive to data verify errors in the write data written into the burst zone, the storage control system writes data associated with the data verify errors into an exception location associated with the burst zone.

Efficient burst data verify in shingled data storage drives

A method of managing critical resource usage comprises monitoring queue depth in at least one critical resource queue for a high level of resource consumption and preventing subsequent commands of a client/server combination in response to a command that increases resource consumption to the high level. The method further comprises queuing an identifier of the client/server combination on a waiting queue, removing the client/server combination identifier from the waiting queue in queuing order as resource consumption declines, and enabling commands of the client/server combination.

Resource management system

A method for easily restoring CMOS parameters in a computer having a multi-function power button is provided. In one embodiment, the method for restoring CMOS parameter values in a computer includes (a) pressing the power button for a predetermined time delay while the computer is performing a power-on self test ('POST'), thereby placing the computer in an OFF state; and (b) momentarily pressing the power button to turn on the computer. Pressing the power button for four seconds preferably invokes a power button override function. The power button override function unconditionally forces the computer to a 'soft-off' state. The BIOS is preferably configured to determine if the power-override function was invoked during the POST in the previous boot-up, and if so, to replace the CMOS parameter values with backup parameter values before proceeding with the current boot-up. The CMOS parameter values are preferably backed up only if they have changed and the BIOS has successfully completed the POST procedure with the changed values. This ensures that the backup values will allow the computer to boot when CMOS parameter restoration is needed.

Method for restoring CMOS in a jumperless system

A computer system for flashing Extended System Configuration Data (ESCD) and associated variables to a flash read-only memory (ROM) is provided. During Power-On-Self-Test (POST) code, a ROM image is copied from an ESCD sector of a read-only memory to an ESCD original buffer and an ESCD write buffer. The ESCD write buffer may be updated by POST code. Following the POST operations, the contents of the ESCD write buffer are copied to an ESCD runtime buffer. The contents of the ESCD original buffer or the ESCD sector are compared to the contents of the ESCD runtime buffer. If the contents of the ESCD runtime buffer differ from the contents of the compared buffer or sector, SMI code flashes the ROM image in the ESCD runtime buffer to the flash ROM. If the ESCD runtime buffer is the same as the contents of the compared buffer or sector, a ROM flash it not performed. POST is then exited and the computer system is booted. During runtime, if a write is performed to ESCD data or an associate variable, the ESCD runtime buffer is updated with the ESCD data or variable provided for the write operation. The SMI code then flashes the ROM image in the ESCD runtime buffer into the ESCD sector to save the ESCD data or variable provided by the write operation.

Method for flashing ESCD and variables into a ROM

A method for easily restoring CMOS parameters in a computer having a multi-function power button is provided. In one embodiment, the method for restoring CMOS parameter values in a computer includes (a) pressing the power button for a predetermined time delay while the computer is performing a power-on self test (&ldquo;POST&rdquo;), thereby placing the computer in an OFF state; and (b) momentarily pressing the power button to turn on the computer. Pressing the power button for four seconds preferably invokes a power button override function. The power button override function unconditionally forces the computer to a &ldquo;soft-off&rdquo; state. The BIOS is preferably configured to determine if the power-override function was invoked during the POST in the previous boot-up, and if so, to replace the CMOS parameter values with backup parameter values before proceeding with the current boot-up. The CMOS parameter values are preferably backed up only if they have changed and the BIOS has successfully completed the POST procedure with the changed values. This ensures that the backup values will allow the computer to boot when CMOS parameter restoration is needed.

A computer system provides a unified password prompt for accepting a user power-on password or an administrator password. A password string entered by the system administrator at the unified password prompt is compared with a stored power-on password. If the user password string matches the stored power-on password, then access to system resources is granted. If the user password string does not match the stored power-on password, then the user password string is compared to a stored administrator password. If the user password string matches the stored administrative password, then access to system resources is granted. If the user password string does not match the stored administrative password, then the system administrator is given a predetermined number of times to enter a password string matching either the stored power-on password or the stored administrator password. If a password string matching either the stored power-on password or the stored administrator password is not provided in the predetermined number of times, access to system resources is denied. The unified password prompt does not require a system administrator to know a user's power-on password in order to access system resources. The unified password prompt also permits a system administrator to configure a plurality of computer systems by providing a single administrative password rather than a plurality of user power-on passwords.

Unified password prompt of a computer system

An apparatus and method to force the computer system to boot from the boot block. During a computer system power-up and initialization, the computer system determines if the escape key is pressed. If so, the computer system will boot from the code in the boot block, proceeding as if the flash ROM is corrupted. This forces the computer system to boot from the boot block even though the system determines that the flash ROM is not corrupt, allowing the user to flash a ROM at the user's discretion.

Growing community of inventors

Cypress, TX, United States of America

Randall L Hess