International Business Machines Corporation

Randall L Henderson

Robert Tamlyn

Nathan R Hiltebeitel

Timothy J Ebbers

Andrew D Bowen

Steven William Tomashot

Satish Gupta

Todd Williams

Michael A Aranda

A random access memory system organized such that multiple pixels may be accessed when one row column address is provided. The random access memory system includes a first group of random access memory devices and a second group of random access memory devices. The first group of devices stores information for pixels on an even horizontal scan line and the second group of devices stores information for pixels on an odd horizontal scan line. An address generator of the random access memory system generates an address to access information from the first group of devices for one pixel and information from the second group of devices for another pixel.

Multi-pixel access memory system

The selection in a dual port memory device of data from a serial access memory register having a lower byte and an upper byte of data is described herein. In one embodiment, the register is partitioned lengthwise into two sections, corresponding to, for example, a frame buffer A and a frame buffer B. On each serial clock cycle, frame buffer A or frame buffer B for each byte of data may be selected from the register. Each of the selected bytes of data are then passed to a serial output port. In another embodiment, the lower byte of data corresponds to, for example, a frame buffer A and the upper byte corresponds to a frame buffer B. Then either the upper byte or lower byte of data is selected to be output on the serial port. In yet a further embodiment, the serial access memory register is partitioned lengthwise into two sections, each section corresponding to, for example, a frame buffer and the bytes of data correspond to another buffer, then either the lower byte or upper byte is selected to be output on the serial port.

SAM data selection on dual-ported DRAM devices

An implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis. The frame buffers are each stored in a portion of a row in a single video RAM. Following data transfer to the serial access memory register, data from each of the two frame buffers is available. A double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal. The serial clock increments the address pointers in both halves of the serial access memory port simultaneously.

Video RAM double buffer select control

An implementation of a serial access memory register facility which allows the external selection of the portion of the SAM to be scanned out. A control signal is provided which causes the reloading of serial access memory address counter causing the reloading of serial access memory address counter causing the serial scanning to shift from one to another of the serial access memory registers. The result is an ability to select a stopping point when scanning out of the serial access memory. Thus, the present invention implements the ability in a video random access memory to specify both the starting and ending points of the data to be scanned out of the serial access memory. The preferred embodiment replaces the QSF status pin with a control pin to preserve the packaging configuration of standard VRAMs.

Growing community of inventors

West Hurley, NY, United States of America

Randall L Henderson