Marvell International Limited

Marvell International Technology Ltd

Hewlett-packard Company

Cypress Semiconductor Corporation

Other

Avago Technologies General IP (singapore) Pte. Ltd.

Marvell Israel (misl) Ltd.

Randall Don Briggs

Douglas G Keithley

Mark David Montierth

David Alan Bartle

Michael D Cusack

Walter Lee McNall

Gary D Zimmerman

Thomas Omega Wheless, Jr

David H Harris

Jay Russell Shoen

Erin Antony Handgen

Richard I Klaus

William B Weiser

William Randolph Schmidt

David Alan Podsiadlo

Greg L Allen

Richard H Benear

Gregory Alton Vaughn

Dave Gilbert

Shankar Kozhumam

Bradley W Cain

Haggai Telem

Frederick Walter Pew

Eran Maor

Douglas G Kiethley

The present disclosure describes apparatuses and techniques for managing aggregate IC current demand. In some aspects, respective indications of first and second amounts of current consumed by IC components are received from the IC. The first and second amounts of current are combined to determine an aggregate current demand for the components of the IC. This aggregate current demand is then compared to a threshold for an amount of current that can be provided to the components of IC. Responsive to the aggregate current demand exceeding the threshold, an operational characteristic of one of the components is modified to reduce the aggregate current demand of the components of the IC. This can be effective to prevent the IC from drawing more current than can by supplied to the IC.

Apparatus and methods for managing aggregate integrated circuit (IC) current demand

Method, algorithms, architectures, packages, circuits, and/or approaches for relatively low cost packaged integrated circuits (e.g., ball grid array or BGA packages) are disclosed. For example, a packaged integrated circuit can include a first chip, the first chip including a plurality of bond pads; a plurality of bond pad connectors in electrical communication with the plurality of bond pads; a substrate having a plurality of layers, at least one of the plurality of layers being configured to electrically connect the plurality of bond pad connectors and a plurality of external package connections; and a redistribution layer on the first chip, wherein the redistribution layer is configured to electrically connect at least one of the plurality of bond pad connectors and at least one of the plurality of bond pads on the first chip.

Ball grid array including redistribution layer, packaged integrated circuit including the same, and methods of making and using the same

Imaging devices incorporating memory are described herein. According to various embodiments, device driver information may be stored in the memory. Subsequent to the device driver being uploaded to a host device and the host device installing the device driver, the device driver information is deleted from the memory of the imaging device.

Storing and removing device drivers in memory in imaging devices

A system including a communication interface, a memory, and a processor. The communication interface is configured to receive data. The memory is divided into a first retention region and a second retention region, wherein the first retention region is configured to store data for a first predetermined period of time, and the second retention region is configured to store data for a second predetermined period of time. The processor is configured to i) initially store, within the first retention region of the memory, the data that is received, and ii) in response to the data that is received having been stored in the first retention region of the memory for a time limit that exceeds the first predetermined period of time, transfer the data that is received from the first retention region of the memory to the second retention region of the memory.

Method and apparatus for optimizing memory usage in an imaging device

Semi-volatile NAND flash memory systems, apparatuses, and methods for use are described herein. According to various embodiments, a semi-volatile NAND flash memory may be partitioned into various retention regions. Other embodiments may be described and claimed.

Method and apparatus for selective use of wear-leveling to store data in a memory

Aspects of the disclosure provide a method. The method includes allocating, by a host computer, a bandwidth of a communication port to a printer that shares the communication port of the host computer with other peripheral devices, generating, by the host computer, a raster page having a file size smaller than a maximum file size, and transferring, by the host computer, the raster page to the printer at the bandwidth to satisfy a print rate of the printer.

Method and apparatus for printing raster page

A circuit verification method for a logic circuit is presented. The method includes developing a first hardware description language (HDL) code representative of the logic circuit and, for an embedded portion of the logic circuit, developing a second HDL code representative of the embedded portion. The second HDL code includes a process of forcing inputs of the embedded portion to one or more known values. The method further includes operating a processing device in conjunction with the first and second HDL codes and verifying operation of the embedded portion in response to forcing the inputs to the logic circuit.

Innovative verification methodology for deeply embedded computational element

Imaging devices incorporating semi-volatile memory are described herein. According to various embodiments, device driver information may be stored in the semi-volatile NAND flash memory. Other embodiments may be described and claimed.

Storing device drivers in imaging devices

A system and method are disclosed for updating data stored in a one-time programmable (non-rewritable) non-volatile storage device ('OTP'). The OTP is segmented so that updated data may be written to unused areas. Valid data may be differentiated from stale data using a data recognition technique such as tallying or indexing. According to a tallying technique, an updated event count may be obtained by counting the number of blown bits in the OTP. Each time the event occurs, the next bit is blown. According to an indexing technique, each bit in an index corresponds to a data block in the OTP. When updated data is written to the next (empty) data block in order in the OTP, the corresponding (next) index bit is blown. A valid data set may be located by counting the number of blown bits in the index.

Updating data in a one-time programmable data storage device

Embodiments of the present disclosure provide a method comprising processing a first pixel of a continuous tone image to generate a first error, the first error representative of a difference between an input level and an output level associated with the first pixel; and in response to processing the first pixel, assigning a random error to a second pixel that is neighboring the first pixel, wherein the assigned random error is independent of the first error. Other embodiments are also described and claimed.

Error propagation during error diffusion halftoning

Embodiments of the present invention provide techniques and configurations for error diffusion halftoning of an image including receiving a signal that indicates selection of a first implementation or a second implementation of determining a threshold perturbation value for error diffusion halftoning of an image, and determining the threshold perturbation value using a table of programmable values according to the selected one of the first implementation or the second implementation, wherein the second implementation provides fewer threshold perturbation values for a larger region of the image than the first implementation. Other embodiments may be described and/or claimed.

Method and apparatus for performing error diffusion among a plurality of pixels of an image during a halftoning process on the image

Method and apparatus for increasing data retention capability of a non-volatile memory

A method and system for generating a halftone image from an input image is disclosed. Visible artifacts caused by the correlation of one or more colors or color planes are avoided because the halftone image analysis for one color affects the halftone image analysis for subsequent colors. A printer controller analyzes at least a part of the input image to dynamically set a sequence of the plurality of colors. Halftone image analysis is carried out in the sequence of the plurality of colors to generate the halftone image.

Pixel stacking avoidance error diffusion halftone

A method and apparatus for performing color plane adjustment are provided. In one embodiment, an apparatus comprises a set of inputs for receiving a first input value and a second input value in a color space. The apparatus also comprises a color plane adjustment component operative to adjust the first input value and the second input value by amounts that depend on a distance of the first input value and second input value, respectively, from a value of neutral gray in the color space. The apparatus further comprises a set of outputs for outputting the adjusted first and second values. A related method and computer program are disclosed. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Method and apparatus for performing color plane adjustment

An integrated circuit includes a first die and a second die positioned in a package. The first die has a redistribution layer formed on the die and including a plurality of relocated bond pads. The relocated bond pads are positioned near an inner edge of the first die that is adjacent to an inner edge of the second die. Each relocated bond pad is coupled to a corresponding bond pad on the second die through a respective bonding wire. The first die further includes a plurality of original bond pads. The redistribution layer further includes at least one intermediate bond pad electrically interconnected through a respective conductive trace to a corresponding original bond pad. Each intermediate bond pad is electrically connected to a corresponding relocated bond pad through a respective bond wire.

Growing community of inventors

Boise, ID, United States of America

Randall Don Briggs