International Business Machines Corporation

Teradici Corporation

Randall Dean Groves

Brett Olsson

Mark A Johnson

Fred Gehrung Gustavson

Ramesh Chandra Agarwal

James Bergheim Shearer

David Victor Hobbs

Martin Stanley Schmookler

Terry L Lyon

John Thomas O'Quin, Ii

Gregory F Grohoski

Mahmut K Ebcioglu

Dennis G Gregoire

David P Tuttle

Method and apparatus for computing resources. One embodiment of the method comprises executing a first application on a computer CPU sub-system during CPU sub-system operation; controlling execution of the first application by an interface coupled to the computer and selectively coupled to the CPU sub-system; generating, by the first application and in response to an event from a user device of the interface, a first image for display; controlling, by the user device and during suspension of the CPU sub-system operation, execution of a second application, on a server coupled to the computer, that generates a second image compressed and transmitted as a compressed image by the server, the interface coupled to the server by a resource selector of the computer, a remote bridge of the computer and the IP network; receiving and decoding, via the remote bridge and during the suspension, the compressed image to generate a display image.

Method and apparatus for providing a hybrid computing environment

A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.

Method and system in a data processing system for loading and storing

A matrix processing unit is described which permits high speed numerical computation. The processing unit is a vector processing unit which is formed from a plurality of processing elements. The Ith processing unit has a set of N registers within which the Ith elements or words of N vectors of data are stored. Each processing element has an arithmetic unit which is capable of performing arithmetic operations on the N elements in the set of N registers. Each vector of data has K elements. Therefore, there are K processing elements. A vector operation of the matrix processing unit simultaneously performs the same operation on all elements of two vectors or more. A subsequent vector operation can be performed within one machine cycle time after the preceding vector operation.

Numerically intensive computer accelerator

A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations. Once the control unit within the SIMD execution unit receives a vector instruction, the control unit translates the instruction into commands for execution by selected processing elements within the SIMD execution unit. If such a vector instruction requires access to memory, a fixed point execution unit within the superscalar processor may be utilized to calculate a memory address which is then utilized by the SIMD execution unit to access memory.

Method and system for providing a single-instruction, multiple-data

An instruction cache design which converts a sequential instruction stream into a compound format in the instruction cache. The conversion from sequential instructions to compound instructions is performed by an instruction stream interpreter unit (ISU), which is placed between the instruction cache and main memory. The conversion process is performed when an instruction cache miss occurs. Each line in the instruction cache contains a single compound instruction. The format of this compound instruction is transparent to programmers and will vary depending on the number of execution units which are to be supported.

Method and apparatus for dynamic conversion of computer instructions

In a vector processing system for processing vector calculations utilizing a portion of a vector comprising a plurality of elements, means for receiving a vector and a vector processing command are provided. The vector processing system also includes means for receiving and storing a start-element value and an end-element value. An arithmetic logic unit is coupled to the means for receiving the vector, the means for receiving the vector processing command, and the means for receiving the start-element and end-element values. The arithmetic logic unit also includes means for executing the vector processing command utilizing only one or more of the elements in the vector, which are selected by the start-element value and the end-element value.

Method and system for vector processing utilizing selected vector

A method and apparatus for improving data processing system performance having a cache. Data from one cache line is easily and quickly copied to another cache line within the cache. In the preferred embodiment, this copy cache line operation is initiated using an opcode of a central processing unit's instruction set. Thus, software running on the data processing system can invoke this cache line copy by executing this CPU instruction. Another feature is the ability to rename a cache line, again using a CPU instruction to initiate the operation. This provides a logical copy of the cache data without having to perform a physical copy.

Method and apparatus for internal cache copy

A controller is coupled to a plurality of registers arranged in an array having a physical configuration of N rows of registers and M columns of registers. A size register within the controller is provided for receiving a selected vector size parameter, which specifies a number of registers comprising a vector register. In response to the vector size parameter, columns in the register array are selected and concatenated to form a vector register having at least a number of registers equal to the vector size parameter. An offset parameter may be utilized to select columns that form a vector register from the M number of columns in the array. Multiple arithmetic logic units, where one arithmetic logic unit is coupled to each row of registers are utilized to perform vector operations. Any register in the array may be utilized to store a vector element or a scalar expression. Vector register lengths, and the number of vector registers, may be dynamically configured by setting the vector size parameter and the offset parameter in the controller.

Method and system for dynamically reconfiguring a register file in a

A data processing system including a circuit for storing a plurality of instructions in a sequence together with a circuit for fetching a plurality of instructions. A circuit is provided for dispatching a plurality of the instructions to one or more processors for execution during a single computation cycle. A control circuit is connected to the dispatching circuit to delay the dispatching of an instruction. when the instruction has an execution result that is dependent upon a previous instruction execution that will set at least one bit in a condition register. The delayed instruction is delayed until that condition register has been accordingly set.

Single cycle dispatch delay in a multiple instruction dispatch mechanism

In a data processing system configured to transfer data in words and an apparatus is provided for manipulating, in response to a single manipulation instruction, the contiguous variable length sequence of data stored in bytes including an instruction decoder for decoding a single manipulation instruction, a memory for storing data in words where each but word includes a plurality of bytes, a circuit responsive to the command signal from the instruction decoder to access a contiguous sequence of the bytes from the memory wherein the first byte of the sequence is not stored on a word boundary, and providing the byte sequence to a plurality of data processing registers wherein the first byte of the sequence is aligned with the first registered boundary. Additionally the apparatus includes the capability to provide the contiguous sequence to memory wherein the first byte of the sequence is not stored on a word boundary. The data sequence maybe specified by the number of bytes in the sequence or by a sequence terminating character.

Apparatus for processing character string moves in a data processing

A data processing system including a data cache with the capability to selectively zero the contents of the data cache. The invention includes a multiplexor arranged to provide a parallel data output that is greater than the parallel data input from either a central processing unit or from a memory that are each connected to access the data cache. This multiplexor is selectively controlled to provide a parallel data output of zeroes upon the decoding of a specific zeroing instruction.

Data cache initialization

A data processing circuit that performs either a merge or Boolean logic operation on data within a single clock cycle in response to an instruction. The circuit includes a control circuit for receiving an instruction during a clock cycle and providing a plurality of control signals in response to the instruction. Data selector circuitry is included for providing a plurality of data words in response to the control signals from the control circuit. Additionally, a rotator is connected to at least one data selector for rotating at least one of the data words in response to a control signal from the control circuit. Logic circuitry is provided for logically combining bits form the rotator and the data selector circuitry in response to control signals from the control circuit for providing data output within the single clock cycle.

Growing community of inventors

Austin, TX, United States of America

Randall Dean Groves