International Business Machines Corporation

Randall Clay Itskin

David Brian Ruth

Yogesh Patgar

Monica Jean Lemay

Vijayalakshmi Krishnamurthy

John Carmine Pescatore, Jr

Kenneth Wayne Todd

Mike Conrad Duron

Anthony DeGroff Drumm

Mark David McLaughlin

Amjad Z Qureshi

Maulin Ishwarbhai Patel

John C Pescatore

Stephen Dale Linam

A method, system, and program product for creating network isolation between virtual machines is provided, including receiving, by a security virtual machine (SVM), an outgoing network packet from a virtual machine (VM). The source internet protocol (IP) address and a source media access control (MAC) address is extracted from the outgoing network packet. A zone identifier table is searched for a zone id, whereby the zone identifier table includes the source IP address and the source MAC address. The outgoing network packet is sent to a physical Ethernet adapter connected to an external network switch whereby the external network switch is connected to an external network, based on the zone id not being found in the zone identifier table. The outgoing network packet is sent to a physical Ethernet adapter that is connected to an internal switch, based on the zone id being found in the zone identifier table.

Creating network isolation between virtual machines

A method, system, and computer program product for improving system performance using cooling configuration information are provided in the illustrative embodiments. A set of components in a data processing system is indexed according to corresponding amounts of cooling available to the components in the set. Priorities are assigned to component users in a set of component users. Using a processor and a memory, a component whose index value represents a higher than threshold amount of cooling availability to the component is allocated to a component user whose priority is higher than a threshold priority.

System performance using cooling configuration information

Accordingly, provided is an apparatus and method for generating a computer system interrupt emulation having the effect of a hardwired interrupt. A service processor with a test circuit interface can be coupled to an integrated circuit, which has a test circuit with an access to a register of the integrated circuit. A program, executable by the processor, responds to an interrupt request by instructing the processor to save a system state of the integrated circuit and to set a system state of the integrated circuit. The method for emulating an interrupt of an integrated circuit provides for receiving an interrupt request. A register of an integrated circuit is then accessed through a test circuit of the integrated circuit. The contents of the register are saved to a storage location, and the register is then set to a state responsive to the interrupt request. The interrupt request may be made locally or remotely.

Apparatus and method for computer system interrupt emulation

A method and system for simultaneous retrieval of snoop address information in conjunction with the retrieval/storing of a cache line load/store operation. The method and system are implemented in a data processing system comprising at least one processor having an integrated controller, a cache external to the at least one processor, and an interface between the at least one processor and the external cache. The external cache includes a tag array and a data array. Standard synchronous static Random Access Memory (RAM) is used for the tag array, while synchronous burst made static RAM is used for the data array. The interface includes a shared address bus, a load address connection and an increment address connection. A cache line load/store operation is executed by placing an address for the operation on the shared address bus, and latching the address with the external cache using a signal from the load address connection. Thereafter, the latched address is incremented in response to a signal from the increment address connection. This allows the shared address bus to be used for execution of snoop operations simultaneously with the retrieval/storage of a cache line load/store operation.

Method and system for simultaneous processing of snoop and cache

A logical bus architecture implements by active devices the functions performed by a physical address/command bus in the context of a multiple processing unit computer system. The logical bus eliminates the electrical loading, and associated frequency limitations, characterizing physical address/command buses as the number of system resources, processing units, connected to the bus increase. Address/command buses from the processing units are individually or in groups connected to ports of an address rebroadcast device. The device also receives bus master information from the computer system arbiter. Since the arbiter information is available before the actual transmission of signals over the address/command buses of the various processing units, bidirectional signal paths in the address rebroadcast device are selectively configured to match the master-slave signal flow between processing units as defined by the arbiter. Address/command signals are received from the master processing unit at one port and appropriately rebroadcast through the other ports to the other processing units with no more than gate propagation delays. Reconfiguration of the port directions in the address rebroadcast device is accomplished with each designation of a new bus master by the arbiter. Not only does the address rebroadcast device eliminate bus loading, but it also facilitates the selective isolation of processing units by port for fault testing and the like.

Logical address bus architecture for multiple processor systems

Apparatus for and methods of detecting an error in multiple state lock step operated circuits. Signatures representing internal states of each circuit are conveyed in daisy chain format to connect successive circuits. Local comparisons between the received signatures and those representing previous internal states are used to detect mismatches between states. Signals indicating the detection of a mismatch appear on a commonly connected error line. Scanned comparison of the circuits to determine those having detected a mismatch allows the error source to be identified.

Validating the synchronization of lock step operated circuits

A computer program is disclosed providing a sequence of automated logic synthesis routines having three phases. Phase I identifies an estimated critical path by assuming optimum allocation within a 'best-fit' preliminary assignment of the technology to a technology-independent model, and optimizes the estimated model for speed. Phase II provides a technology-legal model, and ends by calculating the actual timing provided by the technology-legal model. Phase III uses self-limiting routines, and routines that are unlikely to produce technology violations, to fine tune the production and performance characteristics of the legal model.

Growing community of inventors

Austin, TX, United States of America

Randall Clay Itskin