Zilog, Inc.

Maxim Integrated Products, Inc.

Ixys Ch Gmbh

Randal Quincy Thornley

William James Tiffany

Russell Brent Lloyd

Bruce L Troutman

David Alan Roberts

Gyle Dee Yearsley

Joshua J Nekl

Dale Wilson

A delay-locked loop (DLL) involves a pulse generating circuit that generates first and second pulses from an input clock signal. The second pulse is generated one clock signal period later than the first pulse. The first pulse is supplied to the input of a delay line. An edge of a delayed version of the first pulse as output from the delay line is phase-aligned with respect to a corresponding edge of the undelayed second pulse such that the DLL locks. The sending of pulses through the delay line of the DLL rather than clock signals having more edges per unit time helps reduce DLL aliasing problems and reduces the amount of switching in the delay line, thereby reducing power. consumption. A compact segmented delay line construction allows an input signal of arbitrary wave shape to be delayed by a fraction of the clock signal period.

Pulse matching delay-locked loop

Tampering with an assembly that includes an integrated circuit is detected by measuring a change in at least one property of a conductive molding formed over at least a portion of the integrated circuit. For example, the conductive molding can be a mixture of resin with conductive powder and/or fibers. The molding can be formed as a continuous region or as strips of conductive material. Conductive contacts are positioned to provide and receive current through portions of the conductive material. For example, the property of the molding can be an impedance of a portion of the conductive molding. A significant change in the impedance measured through one or more conductive contacts indicates tampering with the assembly.

Intrusion detection using a conductive material

The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two &#xd7;16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these &#xd7;16 memories, the full address is provided. If the address is within the two columns of the second &#xd7;16 memory, the full address is also provided to the second &#xd7;16 memory. If the address is to the first of the &#xd7;16 memories, the second &#xd7;16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte. The net effect is that all the physical memory physical space is used for program code with none being wasted in the 24-bit access.

Architecture to relax memory performance requirements

Fast electromagnetic transient (EFT) events of short duration are often not detected by power-on reset circuitry of an integrated circuit (IC). A fault detector circuit involves many fault detectors. The fault detectors are distributed across the IC and may be embodied in spare cells left in a standard cell IC. Each fault detector is initialized with a digital logic value. The fault detector circuit is then controlled such that the digital logic value stored should not change if the IC is operated under normal operating conditions. An EFT event that is undetected by the power-on reset circuit may, however, cause one of the digital logic values stored in one of the fault detectors to switch. If the digital logic value stored in any one of the fault detectors switches, then a fault signal is provided to the power-on reset circuit that in turn resets the IC.

Circuit for detection of hardware faults due to temporary power supply fluctuations

The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two &times;16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these &times;16 memories, the full address is provided. If the address is within the two columns of the second &times;16 memory, the full address is also provided to the second &times;16 memory. If the address is to the first of the &times;16 memories, the second &times;16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte. The net effect is that all the physical memory physical space is used for program code with none being wasted in the 24-bit access.

Growing community of inventors

Nampa, ID, United States of America

Randal Quincy Thornley