Northrop Grumman Systems Corporation

Microsoft Technology Licensing, LLC

Randal L Posey

Randall M Burnett

William Robert Reohr

Quentin P Herr

Haitao O Dai

Superconducting logic arrays (SLAs) and field-programmable gate arrays (FPGAs) that are based on Josephson transmission lines (JTLs) accommodate reciprocal quantum logic (RQL) compliant binary input signals and provide RQL-compliant output signals that are evaluations of generalized logic functions. Each JTL-based superconducting FPGA (JTLBSFPGA) incorporates multiple JTL-based SLAs (JTLBSLAs) connected together. Each JTLBSLA includes an array of software-programmable and/or mask-programmed logic cells that output products of inputs and cell states, such that the JTLBSLAs output evaluations of sum-of-products functions. New JTLBSLA logic cells are described, including some that provide programmable cell states via magnetic Josephson junctions (MJJs). JTLBSFPGAs provide area efficiency and clock speed advantages over CMOS FPGAs. Unlike SLAs based on Josephson magnetic random access memory (JMRAM), JTLBSLAs do not require word line drivers, flux pumps, or sense amplifiers. Because JTLBSLAs and JTLBSFPGAs are RQL-compliant, they can also include RQL gates connected within or between them, without signal conversion circuitry.

JTL-based superconducting logic arrays and FPGAS

Current-based superconductor memory cell and related systems and methods are provided. A method in a memory system, having at least one storage circuit and at least one read SQUID, includes applying bit-line current, via a read bit-line not including any Josephson transmission line (JTL) elements, to the at least one read SQUID. The method further includes applying word-line current, via a read word-line not including any JTL elements, to the at least one read SQUID. The method further includes using the at least one read SQUID reading a logic state of the memory cell based on data maintained in the storage circuit.

Memory system with signals on read lines not phase-aligned with Josephson transmission line (JTL) elements included in the write lines

JTL-based superconducting logic arrays and FPGAs

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Randal L Posey