International Business Machines Corporation

Randal Craig Swanberg

Ravi Kumar Arimilli

Satya Prakash Sharma

Bruce Gerard Mealey

Michael Stephen Williams

Naresh Nayar

William Joseph Armstrong

Mark D Rogers

Vishal Chittranjan Aslot

Michal Ostrowski

Orran Yaakov Krieger

Freeman Leigh Rawson, Iii

Steven Leonard Roberts

Brad L Brech

Andre Laurent Albot

Kevin J Reilly

Sunil Jeevananda Kamath

Michael E Daley

Leslie Png

Alise Spence

William John Starke

Lakshminarayana Baba Arimilli

Karthick Rajamani

Charles Scott Graham

Richard Loise Arndt

Kyle Alan Lucke

Cathy May

David Alan Hepkin

Christopher Francois

Christian Jacobi

Bret Ronald Olszewski

Sundeep Chadha

Richard Louis Arndt

Vaijayanthimala K Anand

John David Irish

Mysore Sathyanaranyana Srinivas

Scot H Rider

Steven R Kunkel

Madhusudanan Kandasamy

Mark Robert Funk

Joerg-Stephan Vogt

Andrew T Koch

Vikramjit Sethi

Grover Herbert Neuman

Frank Haverkamp

Ronald Dean Young

Renato John Recio

Hung Qui Le

Steven Mark Thurber

Maged M Michael

Michael Stephen Floyd

Malcolm Scott Ware

Harold Wade Cain, Iii

Bartholomew Blaner

Jose Eduardo Moreira

Gregory Michael Nordstrom

Bradly George Frey

Eric Philip Fried

Diane Garza Flemming

Perinkulam I Ganesh

David Blair Whitworth

Luke Matthew Browning

Khalid Filali-Adib

Miles Robert Dooley

Scott Michael Willenborg

Suresh Eswara Warrier

Benjamin Herrenschmidt

Travis James Pizel

John Thomas O'Quin, Ii

Greg Robert Mewhinney

Frederic Barrat

Stephen Dale Linam

Luc Rene Smolders

Sandy K Kao

Philippe Bergheaud

Luke Mathew Browning

Corene Casper

Priya Ashok Nagpurkar

Jeffrey Scott Peek

Saurabh Nath Sharma

Naresh Nayer

Michael Ostrowski

A processor core of a data processing system, in response to a first instruction, generates a copy-type request specifying a source real address and transmits it to a lower level cache. In response to a second instruction, the processor core generates a paste-type request specifying a destination real address associated with a memory-mapped device and transmits it to the lower level cache. In response to the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to the paste-type request, the lower level cache writes the data granule from the non-architected buffer to the memory-mapped device. In response to receipt of the data granule, the memory-mapped device stores the data granule in a queue in the system memory associated with a hardware device of the data processing system.

Memory move instruction sequence targeting an accelerator switchboard

Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.

Method to share a coherent accelerator context inside the kernel

Intelligent context management for thread switching is achieved by determining that a register bank has not been used by a thread for a predetermined number of dispatches, and responsively disabling the register bank for use by that thread. A counter is incremented each time the thread is dispatched but the register bank goes unused. Usage or non-usage of the register bank is inferred by comparing a previous checksum for the register bank to a current checksum. If the previous and current checksums match, the system concludes that the register bank has not been used. If a thread attempts to access a disabled bank, the processor takes an interrupt, enables the bank, and resets the corresponding counter. For a system utilizing transactional memory, it is preferable to enable all of the register banks when thread processing begins to avoid aborted transactions from register banks disabled by lazy context management techniques.

Intelligent context management

Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. According to one embodiment, a request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.

Systems, methods, and computer program products to perform an operation comprising determining, by a processor, a process identifier of a process associated with a page fault based on an interrupt source number, wherein the page fault was triggered by a coherent accelerator, executing the process on the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.

Resolving page faults out of context

An electronic product can be configured by a method that includes attaching a machine-readable identification (ID) tag containing an ID code to a hardware unit of the electronic product. The ID code is associated with a particular configuration of the electronic product, and can be read or scanned with a mobile device configured to send the ID code to a provider server device. In response to receiving the ID code, the provider server device can send product configuration instructions and a product configuration application to the mobile device. The product configuration instructions can guide a user through a customized series of electronic product configuration operations. The product configuration application can assist the user in performing configuration operations, can provide customized configuration help, and can establish a wireless link between the mobile device and the electronic product, allowing the user to interact with the electronic product.

Customized electronic product configuration

Disclosed aspects include managing the access of flash memory by a computer system. A physical memory address space which includes a flash memory portion is established. The flash memory portion may correspond to an input/output memory range. An access request may be detected with respect to the physical memory address space. Using a load-store technique to process the access request, the flash memory portion of the physical memory address space may be accessed.

Flash memory management

Embodiments disclose techniques for enabling the use poll and select subroutines with coherent accelerator block or character devices. In one embodiment, an operating system receives, from an application, a system call to attach a hardware context with the coherent accelerator block or character device. The operating system generates a channel based on a file descriptor associated with the attach system call. The operating system associates the channel with a hardware context selected from a plurality of hardware contexts available to the coherent accelerator, wherein the hardware context is attached to the application. Upon receiving, from the application, a system call to check for exceptions that have occurred on the coherent accelerator block device or character device, the operating system returns an indication of any exceptions which have occurred while the coherent accelerator was using the hardware context to the application.

Enabling poll/select style interfaces with coherent accelerators

In a data processing system, a switch includes a receive data structure including receive entries each uniquely corresponding to a receive window, where each receive entry includes addressing information for one or more mailboxes into which messages can be injected, a send data structure including send entries each uniquely corresponding to a send window, where each send entry includes a receive window field that identifies one or more receive windows, and switch logic. The switch logic, responsive to a request to push a message to one or more receiving threads, accesses a send entry that corresponds to a send window of the sending thread, utilizes contents of the receive window field of the send entry to access one or more of the receive entries, and pushes the message to one or more mailboxes of one or more receiving threads utilizing the addressing information of the receive entry or entries.

Addressing for inter-thread push communication

Growing community of inventors

Round Rock, TX, United States of America

Randal Craig Swanberg