Motorola Corporation

Rand L Gray

Deepak Mulchandani

Jay A Hartvigsen

John J Vaglica

Nigel J Allison

Alexander L Iles

Michael D Walker

Weilming Sieh

A data processing system (100, 300) allows an individually mappable word of memory to patch a desired memory location. During operation, a memory system (130) monitors an address/control bus to determine when an access to a specified word in a system memory (120) occurs. When an access to the specified word occurs, address comparators (140) determine if a memory location to be patched is being accessed, and provides an active signal to the access control circuit (150), which prevents data flow with the system memory (120) and enables the data flow with a separate memory (170) by controlling a transmission gate 115. Therefore, the data access occurs from the separate memory and not the system memory.

Method and system including memory patching utilizing a transmission

A Target MCU is restored to a Target State. A Host Trace of Debug Commands is preserved as the Target MCU is driven from a known first state to the Target State by executing a series of Debug Commands. The Target MCU is then reinitialized to the known first state. The Debug Commands are read from the Host Trace and sent to a Modular Development System (MDS) for execution by the Target MCU until the Target MCU is again is driven to the Target State.

Method and apparatus for restoring a target MCU debug session to a prior

A Host Debugger and a Modular Development System (MDS) are dynamically reconfigured. The Host Debugger queries the MDS for the identity of its Target MCU. The Host Debugger receives a message containing the Target MCU identity. The corresponding Host Debug and MDS environments are then loaded based on the received Target MCU identity.

Method and apparatus for automatically reconfiguring a host debugger

A parser is dynamically reconfigured. Parse Control Records are read into memory. They are inserted into corresponding Parse Table Entries in a Parse Table in memory identified by a Parse Table Entry Identifier in each Parse Control Record. Each of the Parse Table Entries corresponds to a single command, and includes an ordered series of allowable parse states for that command. After a string of text has been tokenized into an ordered sequence of tokens, the ordered sequence of tokens is evaluated pursuant to the allowable parse states in the Parse Table Entries to determine whether the Text String has a valid syntax.

Method and apparatus for dynamically reconfiguring a parser

A copy of data in a Host Computer is synchronized with a version located in Shared Memory in a Modular Development System (MDS). Whenever a change in one or more bits in a Line of Data in Shared Memory are detected, a MDS Line Dirty Flag is checked. If the Flag is not set, it is set and a message is sent to the Host Computer that the Line of Data is now dirty. Whenever the Host Computer receives this message for a Line of Data in its visible memory, it sends a request to the MDS to read that Line from Shared Memory and send it to the Host. Otherwise, a Host Line Dirty Flag is set. The Host Computer also sends a request to read a Line of Data when that Line of Data is scrolled onto a screen and the corresponding Host Line Dirty Flag is set.

Method and apparatus for synchronizing data in a host memory with data

A data processor with development support features includes an alternate mode of operation in which instructions are received by means of an externally-controlled path. The connections used by the externally-controlled path are not shared by any system resources accessible to the data processor in the normal mode of operation, but are used by other development support features in the normal mode. In a preferred embodiment, an integrated circuit microcomputer includes such a data processor as its CPU. The CPU has access to on-chip peripherals and memory, in addition to off-chip peripherals and memory, in both the normal and alternate modes of operation, by means of a parallel bus which it operates as a bus master. In the alternate mode, the CPU receives instructions by means of a serial bus on which the CPU is a slave device.

Data processor with development support features

A data processing system having a debug peripheral is provided. The debug peripheral is coupled to a central processing unit and memory via an internal communications bus. The debug peripheral is a single-word dual port memory with parallel read-write write access on one side, and synchronous, full-duplex serial read-write access on the other side. The serial side of the debug peripheral is connected to external emulation hardware by means of a three-pin synchronous serial interface. The parallel access is via a connection to a core central processing unit (CPU) internal communications bus. The debug peripheral is addressed at sixteen adjacent locations in the CPU memory space. During a debug interlude, the debug peripheral assumes control of the CPU by providing an interrup signal to the CPU, and thereby causing the CPU to fetch instructions directly from the debug peripheral. The debug peripheral receives instructions from the external emulation hardware, and provides the debug instructions to the CPU, in response to an instruction address provided by the CPU.

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Austin, TX, United States of America

Rand L Gray