Intel Corporation

Cadence Design Systems, Inc.

Ranan Fraer

Gila Kamhi

Amit Gradstein

Ittai Anati

Thierry Pons

Zelig Wayner

Yoad Yagil

Moshe Y Vardi

Osnat Weissberg

Amitai Irron

Marcelo Glusman

Sela Mador-Haim

Adriana Braz

Vince Reynolds

Systems and methods of debugging a design under test (DUT) using formal verification are disclosed. In one aspect, a method includes receiving the DUT from a user and a command to find a counter-example of a liveness property of the DUT and a verification trace including a sequence of states structures as a stem followed by a loop. The method further includes receiving a length of the loop from the user and executing a verification algorithm based on the length of the loop. The method further includes determining that the counter-example is found when the execution of the verification algorithm ends after traversing the stem and the loop.

Method and system for bug finding by checking liveness properties of circuits with formal verification

Embodiments of the present invention provide a processor having an inactive state of operation and methods thereof. The processor, according to some demonstrative embodiments of the invention, the processor may include a controller to determine an inactive state of operation is to be entered, and to cause a predetermined set of one or more execution units to execute a predetermined sequence of one or more micro-operations prior to entering the inactive state. Other embodiments are described and claimed.

Processor having inactive state of operation and method thereof

Briefly, a system and a method of formal verification and failure analysis and rectification of models or designs, e.g., VLSI designs, of processors, circuits and logical systems. Embodiments of the system may include a multi-value annotation scheme for annotating different types of values of signals, and a post-annotation scheme for further analysis based on the annotated values. Some embodiments of the invention may optionally include a generator of counter-examples of a given length.

System and method to analyze VLSI designs

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Haifa, Israel

Ranan Fraer