Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Ran Zamir

Eran Sharon

Alexander Bazarsky

Dudy David Avraham

Idan Alrod

Omer Fainzilber

Stella Achtenberg

Idan Goldenberg

Ofir Pele

Ariel Navon

Rami Rom

Shay Benisty

Yehuda Hahn

Karin Inbar

Tomer Tzvi Eliash

Yan Dumchin

Alon Marcu

Ishai Ilani

Yuri Ryabinin

Yan Li

Tianhong Yan

Amit Kumar Sharma

Amir Shaharabany

Tz-Yi Liu

Evgeny Mekhanik

Abhinandan Venugopal

Xinmiao Zhang

Vinayak Bhat

A Harihara Sravan

Nika Yanuka

Mark Fiterman

Eran Banani

Tsiko Shohat Rozenfeld

Yoav Porat

Igal Mariasin

Stella Achtenburg

Tommer Kuper Lotan

Sanel Alterman

Examples described herein provide a joint LDPC and XOR (JLX) error correction scheme that utilizes parity of the LDPC code to correct errors in XOR stripes of data, allowing improved protection against error. For example, when decoding of a codeword fails, an XOR operation is performed on the other codewords within the same XOR stripe to generate a copy of the failed codeword. The copy of the failed codeword is used as a soft bit input to an LDPC decoder, providing a sense of where errors in the failed codeword may be situated. The LDPC decoder may then recover the failed codeword. The scrambling seed used for encoding pages of data may also be used for recovering from error in a JLX ECC operation.

Data storage device with joint error correction code engines

A multi-gear ECC decoder includes a high power decoder and a low power decoder. In order to significantly reduce the decoding time for high-BER codewords using a slow high power decoder, rather than decoding codewords in either slow high power or fast low power, a controller switches between slow high power decoding and fast low power decoding during the decoding process. The controller first will determine, based on a predetermined factor, whether to start decoding in slow high power or fast low power. Once a decoding power is determined, then the decoding will begin. During the decoding process the decoding transitions from a first power lever decoder to a second power level decoder. The decoding will continue in the second decoding power level after the transition, until the decoding is completed or if another switch needs to occur for insufficient decoding.

ML assisted dynamic decoding gear selection

A state transition matrix for a data storage system indicates a reliability of data that was read or decoded from a data storage channel. The state transition matrix includes a probability of reading each state of a nucleotide base in an identified storage material when that nucleotide base was initially programmed in a particular state. The state transition matrix is generated by identifying a storage material with the most copies in the data storage system. During a sequencing process, the identified storage material is decoded, corrected and compared against the storage material that was originally synthesized. This information is used to determine the probability values for the state transition matrix. The state transition matrix is provided to an error correction system of the data storage system, which uses the probability information when determining whether decoded data of other storage materials should be corrected.

Generating and using a state transition matrix for decoding data in a DNA-based storage system

Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Non-volatile memory die with deep learning neural network

A DNA-based storage system includes an error correction system operable to: (a) identify a DNA codeword from a DNA sequencing operation; (b) calculate an initial syndrome weight; (c) determine that the initial syndrome weight is greater than a predetermined threshold; (d) perform an alignment alteration in the information segment by: (i) selecting a skew point within the information segment; (ii) performing an indel operation on the information segment at the skew point; (iii) calculating a modified syndrome weight; (iv) comparing the initial syndrome weight with the modified syndrome weight; and (v) incorporating the indel operation into the information segment when the comparing indicates an improvement in the modified syndrome weight; (e) decode the modified codeword; and (f) transmit the contents of the output file to a computing device, the output file representing user data stored within the DNA molecule.

Error correction systems and methods for DNA storage

Storage devices are configured to be utilized in a variety of blockchain related activities that rely on a proof of space consensus model. These storage devices are required to process a lot of read and write cycles on their memory devices to generate the desired proof of space consensus data. The generation and storing of this generated data requires very different types of memory device usage. Storage devices may be configured with a first partition for high-speed access for generating the data, while a second partition is also configured for long-term storage of the generated data. As memory devices reach their estimated end-of-life, they can be dynamically reassigned to the second partition. Likewise, some storage devices may be equipped with multiple memory arrays of different types of memory devices. One set of memory devices can be used for generation, while cheaper, write-once or few memory devices are provided for storage.

Cold storage partition management in proof of space blockchain systems

A DNA-based storage system implements a sub-code architecture for error correction capability (ECC) purposes. The sub-code architecture enables a long DNA strand to be divided into two or more short DNA strands. Each short DNA strand has its own unique parity information. Additionally, each short DNA strand is separately decodable from the other short DNA strands. The parity information associated with a particular short DNA strand is used to correct any errors that occur or are detected during the decoding process. However, if the decoding and error correction processes are not successful using the parity information associated with the particular short DNA strand, global parity information is used to decode the particular short DNA strand and correct the errors. Global parity information includes information from each short DNA strand and the parity information associated with each short DNA strand.

DNA storage error correction code architecture for optimized decoding

A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.

Data storage device with efficient decoder pool and method for on-the-fly decoder initialization

A DNA-based storage system uses a set of initial state transition probabilities during a decoding process in which a DNA codeword is decoded. After a threshold number of decoding iterations of the decoding process have been executed, at least one initial state transition probability of the set of initial state transition probabilities is updated. The at least one initial state transition probability is updated based, at least in part, on information obtained during the threshold number of decoding iterations. When the at least one initial state transition probability is updated, the decoding process resumes and uses the updated at least one initial state transition probability.

Calibrating state transition probabilities associated with a DNA-based storage system to optimize decoding

The present disclosure generally relates to data storage devices, such as solid state drives. A data storage device includes a controller, one or more volatile memory locations, and one or more non-volatile memory locations. Computations, including reinforcement learning algorithms, may be completed by the controller using the one or more non-volatile memory locations. Data associated with reinforcement learning is stored in a table on one or more planes of the non-volatile memory, where the results from the computations update the table with the relevant values. The data in the table are aligned to one or more wordlines, such that sensing the wordline senses all the data stored in the table.

Memory device with reinforcement learning with Q-learning acceleration

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service.

Storage system and method for inference of read thresholds based on memory parameters and conditions

Storage devices are configured to be utilized in a variety of blockchain related activities that rely on a proof of space consensus model. These storage devices are required to process a lot of read and write cycles on their memory devices to generate the desired proof of space consensus data. The generation and storing of this generated data require very different types of memory device usage. As these operations increase in popularity, the need to segment storage devices meant for proof of space usage and those which are not becomes more important. Storage devices may be configured to throttle these different usage types upon detecting these proof of space blockchain activities. Throttling may include reducing clock frequencies, selecting slower performing trim parameters, and programming memory devices with a reduced voltage window, among other processes. Detecting whether throttling should commence, or end can be done via a deployed machine learning classifier.

Storage device throttling in proof of space blockchain systems

The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

On-chip non-volatile memory (NVM) search

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a search command from a host device, where the search command is for value associated with a key value (KV) format having a specific sequence, prepare one or more search buffers and send the one or more search buffers to the memory device, retrieve one or more wordlines having KV pair data associated with the KV format, where the KV pair data includes a key and a value, compare the retrieved one or more wordlines with the one or more search buffers for values having the specific sequence, and provide at least a portion of the value from one or more KV pair data based on the comparing to the host device.

Storage media based search function for key value data storage devices

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to segment a key to physical (K2P) table into two or more segments, wherein each segment of the two or more segments corresponds to a caching priority of key value (KV) pair data, organize the K2P table by storing and relocating one or more K2P table entries into a respective segment of the two or more segments, wherein the storing and relocating comprises moving a K2P table entry based on the caching priority of the KV pair data into the respective segment having the caching priority, and utilize the K2P table to manage KV pair data stored in the memory device, wherein utilizing the K2P table comprises applying a same management operation, such as prefetching, to each K2P table entry of a same segment.

Growing community of inventors

Ramat Gan, Israel

Ran Zamir