Intel Corporation

Ran Shimon

Elan Banin

Roy Amel

Ofir Degani

Ashoke Ravi

Rotem Banin

Eng Hun Ooi

Igal Kushnir

Eytan Mann

Shahar Porat

Amir Israel Rubin

Shahar Gross

Nati Dinur

Yossi Tsfati

Ayal Eshkoli

Ronen Gernizky

Vladimir Volokitin

Elinor Kashani

Dmitry Felsenstein

Qinghua Li

Robert J Stacey

Xiaogang Chen

Assaf Gurevitz

Ilan Sutskover

Tzahi Weisman

Tal Davidson

Ofer Benjamin

Slava Vaysman

Nurit Spingarn

Tai Davidson

Roy Nahum

Yuval Dafna

An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

Time encoded data communication protocol, apparatus and method for generating and receiving a data signal

A communication circuitry device for correcting a phase imbalance, the communication circuitry device comprising one or more processors configured to estimate a non-linear component of a reference signal based on a measurement of a tone at a first harmonic of a plurality of harmonics of the reference signal, estimate an in-phase component of the reference signal based on subtracting the non-linear component from a measurement of a tone at a second harmonic of the plurality of harmonics of the reference signal, and generate a calibration signal based on the estimation of the in-phase component.

Methods and devices generating a calibration signal for an IQ imbalance

A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.

Digital phase locked loop frequency estimation

A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.

The present disclosure relates to a transmitter for transmitting a transmit signal comprising a first signal portion and a second signal portion. The transmitter comprises a power amplifier configured to amplify the transmit signal. The power amplifier is prone to undesired gain variations during the first and the second signal portion. The transmitter further comprises a transmit feedback receiver coupled to an output of the power amplifier and configured to feed back the transmit signal to generate a fed back first signal portion and a fed back second signal portion. Processing circuitry is configured to determine a first gain relation between the fed back first signal portion and the first signal portion and to determine at least one second gain relation between the fed back second signal portion and the second signal portion. Power adjustment circuitry is configured to adjust a transmit power of the transmit signal according to a variation between the first gain relation and the second gain relation.

Apparatuses and methods for transmitting a transmit signal comprising a first signal portion and a second signal portion

This disclosure describes methods, apparatus, and systems related to early indication system. A device may identify a high efficiency frame in accordance with a high efficiency communication standard, received from a first device, the high efficiency frame including, at least in part, one or more legacy signal fields and one or more high efficiency signal fields. The device may determine a length field included in one of the one or more legacy signal fields, wherein the length field includes an indication bit. The device may determine a position of a high efficiency short training field within the high efficiency frame based at least in part on the indication bit.

Early indication for high efficiency fields

Described herein are technologies related to an implementation of a closed-loop system to measure and compensate non-linearity in a transceiver circuitry of a device.

Pre-distortion calibration

A digital phase locked loop operates with a time-to-digital converter and an a-priori-probability-phase-estimation component or estimator component that estimates the un-quantized phase associated with a quantization output of the time-to-digital converter. The time-to-digital converter generates a quantized value as the quantization output from a local oscillator signal of a local oscillator and a reference signal of a reference clock. The estimation component estimates a phase value from the quantized values as a function of a-priori data related to the time-to-digital converter and boundaries of the quantized value.

A-priori-probability-phase-estimation for digital phase-locked loops

Growing community of inventors

Ramat Gan, Israel

Ran Shimon