Mellanox Technologies, Ltd.

Mellanox Technologies Tlv Ltd.

Mellanox Technologies Denmark Aps

Ran Sela

Liron Mula

Ran Ravid

Oded Wertheim

Thorkild Franck

Roy Kriss

Ulrik Wismar

Dotan David Levi

Shai Cohen

Johan Jacob Mohr

Guy Lederman

Yaniv Strassberg

Chen Gaist

Aviv Berg

Dotan Finkelshtein

Eyal David

Stanislav Gurtovoy

Aviv Hasson

Daniel Kedar

Afek Bernhard

In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.

Receive-side timestamp accuracy

An Integrated Circuit (IC) includes functional circuitry and attack-protection circuitry (APC). The functional circuitry is to receive a supply voltage from a power-supply input. The APC is coupled to the power-supply input and includes a front-end circuit and an averaging circuit. The front-end circuit is to compare the supply voltage to a plurality of voltage thresholds, and to output a respective plurality of indications that indicate whether the supply voltage violates the respective voltage thresholds. The averaging circuit is to estimate, for a selected subset of the indications, respective duty-cycles at which the indications in the subset exceed the respective voltage thresholds. The APC is to trigger one or more attack detection events in response to the indications and the duty-cycles.

Protection against attacks on integrated circuits using voltage monitoring

An Integrated Circuit (IC) includes a digital phase-locked loop (DPLL) circuit and DPLL Diagnostics circuitry (DPLL-DC). The DPLL circuit includes an oscillator, a digital phase detector and a digital feedback bus (DPLL-DFB). The oscillator is configured to generate an output signal. The digital phase detector is configured to generate a digital feedback signal indicative of a phase difference between the output signal and a reference input signal. The DPLL-DFB is configured to feed-back the digital feedback signal for controlling the oscillator. The DPLL-DC is coupled to the DPLL-DFB and is configured to monitor events depending at least on the digital feedback signal transferred on the DPLL-DFB.

Test circuit for a digital phase-locked loop

Methods and apparatuses are provided for locking a transmitter oscillator to a reference clock signal in a frequency domain. The apparatus includes a digital phase-frequency detector. The digital phase-frequency detector includes a mod-M counter, a mod-N counter, and a count evaluation digital circuit. The mod-M counter is designed to count reference clock cycles of a reference clock signal. The mod-N counter is designed to count local clock cycles of a local clock signal. The count evaluation digital circuit is designed to compare the counted reference clock cycles and the local clock cycles with a predefined register setting to generate a control signal as a feedback signal. The control signal is transmitted to the transmitter oscillator through a frequency-locked loop circuit for adjusting the frequency of the transmitter oscillator to be consistent with the reference clock signal.

Method and apparatus for locking a transmitter oscillator to a reference clock signal in a frequency domain

Embodiments are disclosed for channel estimation in a receiver of a communication system. An example method includes receiving, via a receiver of a communication system, an input signal. The example method further includes using a first event indicator embedded in an analog circuit of the receiver to slice the input signal to generate a sliced input signal and applying an offset to the input signal to generate an offsetted signal. The example method further includes using a second event indicator embedded in the analog circuit to slice the offsetted signal to generate a sliced offsetted signal. The example method further includes applying a first predefined delay to the sliced input signal and applying a second predefined delay to the sliced offsetted signal. The example method further includes generating a conditional ones signal based on the sliced input signal and the sliced offsetted signal and using the conditional ones signal to calibrate an equalizer embedded in the receiver.

Method and apparatus for blind channel estimation

Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.

Data forwarding with speculative error correction

Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block.

Error correction on demand

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Giv′at-Shmuel, Israel

Ran Sela