Samsung Electronics Co., Ltd.

Ramzi Ammari

Changho Choi

Zongwang Li

Rajinikanth Pandurangan

Yang Seok Ki

Praveen Krishnamoorthy

Mukesh Garg

Systems and methods for memory representation and management are disclosed. A request to allocate memory in a first storage medium is identified. The first storage medium may be associated with a first tier of a memory hierarchy. The memory may be represented via at least a first node of a first data structure in response to the request. The first data structure may be associated with the first tier. Activity associated with a memory address represented by the first node may be tracked, and an order for the first node in the first data structure may be updated based on the activity. An association of the first node may be moved from the first data structure to a second data structure. The second data structure may be associated with a second tier of the memory hierarchy.

Systems and methods for memory representation and management

Systems and method for memory representation and tracking are disclosed. A storage system may identify a request to allocate memory in a first storage medium. In response to the request, the storage system may represent the memory via at least a first node of a first data structure. The first node may store first information for a first portion of the memory and a second portion of the memory. A criterion may be monitored for at least one of the first portion or the second portion. An order of the first node in the first data structure may be updated based on detecting the criterion.

Systems and methods for memory representation and tracking

A system is disclosed. The system may include a processor. The system may also include a first submission queue (SQ) and a second SQ. The first SQ may be associated with a first Quality of Service (QoS) level and the second SQ may be associated with a second QoS level, the first QoS level being different from the second QoS level. An application may be running on the processor and using a first namespace (NS). The processor may be configured to receive a first Non-Volatile Memory (NVM) Set create command to establish a first NVM Set associated with the first SQ. The processor may be further configured to receive a second NVM Set create command to establish a second NVM Set associated with the second SQ. The processor may be further configured to receive a first NS create command to establish a first NS associated with the first NVM Set. The processor may be further configured to receive a second NS create command to establish a second NS associated with the second NVM Set. The processor may be further configured to place an input/output (I/O) request sent from the application to at least one storage device in the first SQ based at least in part on the I/O request being associated with the first NS, the first NS being associated with the first NVM Set, and the first NVM Set being associated with the first SQ.

System architecture providing end-to-end performance isolation for multi-tenant systems

A system is disclosed. A computational storage unit may include a memory and a tool. A command parser may receive a command and start the tool on the computational storage unit. A pipe may be established between a file in the memory and an input of the tool.

Interactive mechanism to communicate with tools inside computational devices

Systems and methods for mapping a location in a source code to a location in a machine code are disclosed. An identifier of the source code and an identifier of a first location of the source code are received. A marker is inserted in association with the source code based on the identifier of the first location. The source code is compiled into machine code. A second location associated with the marker is identified in the machine code. A third location is returned based on identifying the second location.

Systems and methods for automapping source code to machine code

A storage device is disclosed. The storage device may include a storage for a data and a controller to process an input/output (I/O) request from a host processor on the data in the storage. A computational storage unit may implement at least one service for execution on the data in the storage. A command router may route a command received from the host processor to the controller or the computational storage unit based at least in part on the command.

Universal mechanism to access and control a computational device

A host interface layer in a storage device is described. The host interface layer may include an arbitrator to select a first submission queue (SQ) from a set including at least the first SQ and a second SQ. The first SQ may be associated with a first Quality of Service (QoS) level, and the second SQ may be associated with a second QoS level. A command fetcher may retrieve an input/output (I/O) request from the first SQ. A command parser may place the I/O request in a first command queue from a set including at least the first command queue and a second command queue. The arbitrator may be configured to select the first SQ based at least in part on a first weight associated with the first SQ and a second weight associated with the second SQ. The first weight may be based at least in part on a first total storage capacity of at least one first namespace (NS) associated with the first QoS level, and the second weight may be based at least in part on a second total storage capacity of at least one second NS associated with the second QoS level.

Binding application to namespace (NS) to set to submission queue (SQ) and assigning performance service level agreement (SLA) and passing it to a storage device

Growing community of inventors

Santa Clara, CA, United States of America

Ramzi Ammari