Intel Corporation

Ramya Yeluri

Dheeraj R Subbareddy

Ankireddy Nalamalpu

Mahesh K Kumashikar

Atul Maheshwari

Arun Jangity

Systems or methods of the present disclosure may provide a programmable logic device including multiple logic array blocks each having multiple programmable elements. The multiple logic array blocks are arranged in multiple rows that are segmented into multiple segments. The programmable logic device also includes repair circuitry disposed between the multiple segments. The repair circuitry remaps logic within a first segment of the multiple segments when a first logic array block of the multiple logic array blocks has failed. Moreover, the first segment includes the first logic array block.

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Mountain View, CA, United States of America

Ramya Yeluri