Forza Silicon Corporation

Aptina Imaging Corporation

Ramy Tantawy

Barmak Mansoorian

Guang Yang

Daniel A Van Blerkom

Steven Huang

A system that has plural different photodetector circuits, each photodetector circuit including its own transfer gate, and each of the plural different photodetector circuits and transfer gates commonly connected to a first node. In amplifier is used which maintains a fixed voltage edits input. The amplifier Has a first capacitance to ground in a second capacitance as a feedback between its output and input. In one embodiment, there are 16 photodetector circuits connected to the single amplifier. In embodiments, the photodetector circuits can be located in one substrate while the amplifier is located in another substrate, and the amplifier also minimizes parasitics between the substrates.

Pinned charge transimpedance amplifier

An imaging device and method for operating the imaging device. Some embodiments comprise a pixel array configured as rows and columns of binning pixel units, each binning pixel unit including a plurality of photosensors that generate respective charge signals in response to incident light. Each binning pixel unit is configured to selectively bin the charge from at least two of the photosensors. The pixel array may be readout in a binning-pixel-unit row by binning-pixel-unit row basis. During readout of each binning pixel unit row, each binning pixel unit in the row is operable to selectively bin at least two of the charge signals therein based on a respective one of control signals provided to each of the binning pixel units in the row. In reading out a binning pixel unit row for a given image frame, a first binning pixel unit may perform in-pixel charge domain binning while a second binning pixel unit in the row may not bin the charge from the different photosensors therein. The respective control signals may be provided as a reset control signal coupled to the binning pixel units via respective vertical reset control lines, each of which is coupled to all of the binning pixel units in a respective column of binning pixel units, each reset control signal being operable to cause potential level resetting of a charge storage region in the binning pixel cell.

CMOS image sensor with column-wise selective charge-domain binning

A successive approximation A/D converter which includes a sub ranging classifier that receives an input signal and classifies said input signal according to plural different highest resolution bits, to determine a range of the input signal, and creating a set of most significant bits based on said range, said subranging classifier also setting and determining an offset based on said range, and a successive approximation A/D converted that converting lowest resolution parts of the input signal as adjusted by the offset.

Segmented column-parallel analog-to-digital converter

Embodiments of the invention comprise methods, apparatuses and systems for a dynamic bias control circuit configured to dynamically bias an amplifier. The dynamic bias control circuitry includes four branches. Each of the four branches includes a transistor operably coupled in series between a current source and a reference voltage. Each branch also includes a storage element having a first terminal and a second terminal and configured for selectively coupling the first terminal to the reference voltage, selectively coupling the first terminal to a node located between the current source and a drain of the transistor, selectively coupling the second terminal to the node, and selectively coupling the second terminal to an output.

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Pasadena, CA, United States of America

Ramy Tantawy