Mediatek Corporation

Mediatek Singapore Pte. Ltd.

Broadcom Corporation

Ramy Awad

Tamer Mohammed Ali

Afshin Momtaz

Namik Kocaman

Adesh Garg

Anand Jitendra Vasani

Ullas Singh

Henry Arnold Park

Miguel Gandara

Mohammed Abdul-Latif

E-Hung Chen

Amr Amin Hafez Amin Abou-El-Sonoun

Ahmed Othman Mohamed ElShater

Miguel Francisco Gandara

Ahmed Othman Mohamed El Shater

A low power receiver having a feedforward equalization, FFE, based continuous time linear equalizer, CTLE. The FFE CTLE comprises: an input for receiving an input signal; a main first path operably coupled to the input and comprising a source-follower transistor arranged to apply a scaling factor to the received input signal; a second path operably coupled to the input and comprising a delay arranged to apply a delay to the received input signal and a common source transistor common source transistor arranged to apply a scaling factor to the received delayed input signal, wherein the source-follower transistor and the common source, CS, transistor are connected as a single SF-CS stage whose output is arranged to subtract the output of the common source transistor from an output of the source-follower transistor.

Low power receiver with equalization circuit, communication unit and method therefor

A receiver front-end includes a first variable-gain amplifier that performs attenuation; a continuous time linear equalizer coupled to the input or output of the first variable-gain amplifier, wherein a combination of the first variable-gain amplifier and the continuous time linear equalizer produces a processed signal; a plurality of track-and-hold circuits that sample the processed signal in an interleaved manner; and a plurality of second variable-gain amplifiers receiving input signals from the plurality of track-and-hold circuits respectively.

Hybrid receiver front-end

A line receiver is described. The line receiver may be configured to receive signals transmitted via a communication channel, such as a metal trace on a printed circuit board or a cable. The receiver may comprise a buffer and circuitry for enhancing the trans-conductance gain of the buffer. By enhancing the trans-conductance gain of the buffer, linearity may be improved and susceptibility to process and temperature variations may be limited. Enhancement of the trans-conductance gain may be performed using feedback circuitry coupled to the buffer. The receiver may further comprise mirror circuitry configured to provide a desired current to the load. The receiver may further comprise a gain stage for setting the gain of the receiver to a desired level.

Low-voltage high-speed receiver

A line receiver comprising a switched capacitor circuit and a buffer is described. The buffer may be configured to receive, through the switched capacitor circuit, an analog signal. In response, the buffer may provide an output signal to a load, such as an analog-to-digital converter. The switched capacitor circuit may be controlled by a control circuitry, and may charge at least one capacitive element to a desired reference voltage. The reference voltage may be selected so as to bias the buffer with a desired DC current, and consequently, to provide a desired degree if linearity. The line receiver may further comprise a bias circuit configured to generate the reference voltage needed to bias the buffer with the desired DC current.

Switched-capacitor buffer and related methods

A line receiver including an analog-to-digital converter is described. The line receiver may include an input stage, a first sampling stage, an integration stage, and a second sampling stage. The input stage may be configured to receive an input voltage representative of a signal transmitted by a transmitter, and to convert the input voltage to a current. The input stage may include a trans-conductance stage. The current may be sampled using the first sampling stage. The sampled current may be converted to a voltage using the integration stage. The integration stage may include a trans-impedance stage. The voltage obtained using the integration stage may be sampled using the second sampling stage.

Multiple sampling stage receiver and related methods

A low-power high-swing current-mode logic (CML) driver circuit includes a first differential-pair and a second differential-pair. The first differential-pair includes first transistors, and is coupled to a first voltage supply that supplies a first voltage. The second differential-pair includes second transistors, and a common node of the second differential-pair is coupled to a second voltage supply. The second voltage supply supplies a second voltage that is higher than the first voltage. Control terminals of the first transistors are coupled to control terminals of the second transistors to form input nodes of the driver circuit.

Low-power high swing CML driver with independent common-mode and swing control

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Irvine, CA, United States of America

Ramy Awad