National Semiconductor Corporation

Texas Instruments Corporation

Ramsin Michael Ziazadeh

Jitendra Mohan

Vijaya G Ceekala

Xin Liu

Varadarajan Devnath

Abu-Hena Mostafa Kamal

Chen-Lun Yen

Yongseon Koh

Devnath Varadarajan

Laurence Douglas Lewicki

James B Wieser

Matthew James Webb

Ashwin Ramachandran

Babak Matinpour

Anindita Borah

Vjay Ceekala

Hesam Aslan

In an example, a circuit includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal. The differential input circuit includes a first transistor having a first transistor control terminal and first and second terminals. The differential input circuit includes a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together. The circuit includes a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal. The circuit also includes a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal. The circuit includes a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal.

Sampler circuit for high speed serializer/deserializer

An integrated circuit (IC) includes a voltage-to-current converter circuit having a first voltage terminal, a second voltage terminal, a first current terminal, and a second current terminal. A transimpedance amplifier (TIA) and biquad filter circuit has a first TIA and biquad filter input coupled to the first current terminal and has a second TIA and biquad filter input coupled to the second current terminal. The transimpedance amplifier includes cross-coupled transistors configured to use positive feedback.

Clock distribution with transimpedance amplifier and biquad filter

A circuit includes a voltage-controlled oscillator (VCO) and a frequency divider. The frequency divider input is coupled to the VCO output. The circuit further includes a phase-frequency detector (PFD). A control output of the PFD is coupled to the VCO. A first PFD input is coupled to a first frequency divider output, and a second PFD input is coupled to a second frequency divider output. The first frequency divider output is configured to provide a first frequency divider signal and the second frequency divider output is configured to provide a second frequency divider signal 90 degrees out of phase with respect to the first frequency divider signal. The PFD is configured to detect an occurrence of at least two edges of a signal on the data input while the second frequency divider signal is continuously logic high across the at least two edges.

Clock data recovery

A driver assistance system includes a first camera, a second camera, a first serial interface circuit, a second serial interface circuit, and a hub interface circuit. The first serial interface circuit is coupled to the first camera. The second serial interface circuit is coupled to the second camera. The hub interface circuit is coupled to the first serial interface circuit and the second serial interface circuit. The hub interface circuit is configured to receive transmissions from the first serial interface circuit and the second serial interface circuit, and to transmit control information to the first serial interface circuit and the second serial interface circuit. The hub interface is also configured to encode a clock signal in the control information.

Multi-camera synchronization through receiver hub back channel

A method and apparatus for a Gigabit Ethernet transceiver that has a Class-B amplifier in a main transmitter for higher efficiency and power handling capabilities. The output current of the main transmitter is produced by a reference voltage applied across a resistor, where the reference voltage generator, resistor and amplifier are fabricated on the same substrate, such that the output current is constant across process voltage and temperature. The transceiver also has a replica transmitter whose signal is used to cancel the main transmitter signal at the input of the receiver section of the transceiver. The replica transmitter is fabricated on the same substrate as the main transmitter, such that its output signal reflects non-linearities in the main transmitter across process voltage and temperature.

Class-B transmitter and replica transmitter for gigabit ethernet applications

A communications cabling front-end architecture that achieves solid echo cancellation and lower noise performance by combining an echo-cancellation circuit and an equalizer function at the same point, at the most front-end of the system.

Apparatus and method for automatic gain control and echo cancellation in a network system

An integrated circuit comprises a pin coupled to receive signals from outside the integrated circuit and an input network. The input network equalizes incoming signals by attenuating lower frequency input signals more than higher frequency input signals received at the pin. The input network is configured to generate a DC bias voltage at an output of the input network in response to an AC coupled input signal or a DC coupled input signal received at the pin with a wide common-mode range.

All-pass termination network with equalization and wide common-mode range

A driver for a vertical-cavity surface emitting laser (VCSEL) is provided that includes a bias current source, a modulation current source, and an output tracking circuit. The bias current source is operable to generate a bias current and an output voltage for the VCSEL and to generate a replica output voltage. The modulation current source is coupled to the bias current source by at least one switch and is operable to generate a modulation current for the VCSEL when the switch is closed. The output tracking circuit is coupled to the bias current source. The output tracking circuit is operable to generate a feedback signal for the bias current source based on the output voltage and the replica output voltage. The bias current source is also operable to generate the output voltage and the replica output voltage based on the feedback signal.

Driver for vertical-cavity surface-emitting laser and method

A circuit and method for comparing and providing a signal indicative of a difference in magnitude between a differential signal voltage and a differential reference voltage.

Differential voltage comparator

A driver for a vertical-cavity surface emitting laser (VCSEL) is provided that includes a bias current source, a modulation source, and a peaking control circuit. The bias current source is operable to generate a bias current for the VCSEL and an output voltage. The modulation current source is coupled to the bias current source by at least one switch and is operable to generate a modulation current for the VCSEL when the switch is closed. The peaking control circuit is coupled to the bias current source. The peaking control circuit is operable to receive the output voltage from the bias current source and to generate a driver output voltage for the VCSEL based on the output voltage. The driver output voltage has less peaking than the output voltage.

System for controlling peaking for a driver for a vertical-cavity surface-emitting laser

A system and a method are disclosed for providing a constant swing high-gain complementary differential limiting amplifier. High gain for the differential amplifier is created by providing a current to the driving transistors that is a combination of any of (a) constant current, (b) transconductance based current, and (c) temperature compensated based current. A constant differential output swing is created by providing a varying differential current to the output load resistors of the differential amplifier that tracks process and temperature variations within the output load resistors.

System and method for providing a constant swing high-gain complementary differential limiting amplifier

An input network is provided within an integrated circuit for interfacing with signals produced by an external CML driver apparatus. The input network includes an input for receiving the signals, and this input is coupled to a terminating impedance, a DC attenuator and an AC attenuator. A common-mode correction loop is coupled to the AC attenuator and the DC attenuator for rejecting common-mode noise generated by the CML driver apparatus. The common-mode correction loop can also provide a common-mode voltage suitable for facilitating high-speed operation of low-voltage devices in the internal data path of the integrated circuit. An amplifier can be provided to compensate for signal attenuation in the input network.

Growing community of inventors

San Jose, CA, United States of America

Ramsin Michael Ziazadeh