Intel Corporation

Ramprasad Satagopan

David R Regenold

N Gopalan Nair

Parviz Hatami

Marc Jalfon

Franco Ricci

A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space. This permits the program code to be loaded into any available page, and the processors can execute the code regardless of where it has been loaded, thereby permitting easy relocatability.

Method to share memory in a single chip multiprocessor system

Memory address translations for programs code execution/relocation

Paged memory architecture for a single chip multi-processor with

An interrupt processor controller (IPC) through which all interprocessor interrupts are routed in a complex integrated circuit. For processors which receive external interrupts, the interrupt processor controller may receive those interrupts and route those as well to the particular processor. The IPC includes interrupt routing logic which determines when a subsequent interrupt will cause an error condition with a previously instigated interrupt that has not been cleared. When such a condition occurs, a bit is set in an error detect register that is coupled to the interrupt routing logic. All of the bits of the error detect register are logically OR'ed, the output of which is routed to a single dedicated pin for indicating an interrupt error condition has occurred. This pin may have its signal routed back into the complex integrated circuit for signaling a trap handler or some other mechanism that an interrupt error condition has occurred. During debug, the error detect register may be checked to determine which bit has been set wherein each bit corresponds to a single interprocessor interrupt channel. Thus, the location of the interrupt error in the executing code can be determined and provide the system developer with important information for the debug of the system.

Error condition detector for handling interrupt in integrated circuits

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Chandler, AZ, United States of America

Ramprasad Satagopan