Cisco Technology, Inc.

Ramprasad Nagaraja Rao

Pirabhu Raman

Hariharan Balasubramanian

Deepak Cherian

Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read or write access is increased by partitioning a memory into a group of sub-blocks, associating a parity block with the sub-blocks, and accessing the sub-blocks to read data as needed. Write access is increased by including a latency cache that stores data associated with a read command. Once a read-modify write command is received, the data stored in the data cache is used to update the parity block. In a memory without a parity block, write access is increased by adding one or more spare memory blocks to provide additional memory locations for performing write operations to the same memory block in parallel.

Executing parallel operations to increase data access performance

In one embodiment, a method includes receiving a packet at an input port of a network device, the input port having a plurality of queues with at least one queue for each output port at the network device, identifying a port group for transmitting the packet from the network device, the port group having a plurality of members each associated with one of the output ports, and selecting one of the queues based on utilization of the members. An apparatus for load balancing is also disclosed.

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San Jose, CA, United States of America

Ramprasad Nagaraja Rao