3com Corporation

3 Com Corporation

The Lan Guys, Inc.

Ramon S Co

Ron Kao

Richard L Traber

A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.

Phase detector which eliminates frequency ripple

A digital phase-locked data recovery circuit having improved noise immunity. The data recovery circuit includes a multi-phase clock for supplying clock signals having a predetermined relative phase relationship. A snap shot sampling network takes samples of an input data signal in response to the multi-phase clock signals. The samples are preferably collected during the duration of boundary sampling windows encompassing transitions in the input data signal. The present invention further includes a network for comparing the received data samples with a sample pattern. A phase encoder then generates error signals in response to the phase comparisons. A phase decoder adjusts the phase of the boundary window in response to the error signal.

Digital phase-locked data recovery circuit

A timing recovery scheme disposed to be substantially invariant to the specific composition of an input data sequence. The phase detection network of the present invention will typically be addressed by a data waveform having a plurality of data packets separated by data delimiters. In operation, the phase detection network of the present invention generates a phase error signal in response to the phase difference between a binary data waveform and a periodic clock waveform recovered therefrom. The inventive phase detection network includes a shift register for storing samples of the incident data waveform. The contents of the shift register are monitored by a boundary detection circuit disposed to signal the presence of one of the delimiters within the shift register. Upon detection of such a delimiter a boundary correction circuit is disposed to generate a phase detection enable signal. The inventive phase detection network further includes a phase detector which is operative, upon being enabled by the boundary correction circuit, to compare the relative phase between the data and clock waveforms in order to synthesize the phase error signal.

Method and apparatus for pattern independent phase detection and timing

An improved circuit topology for implementing level detection and data restoration operations on an input sinusoid. The differential high-frequency level detector and data restoration circuits of the present invention each include a differential input having a pair of circuit nodes for receiving a differential input signal. A slicing offset network is disposed to generate first and second differential signals in response to the differential input signal. The present invention further includes first and second comparators for respectively providing latch set and latch reset signals in response to the first and second offset differential signals. The data restoration circuit of the present invention further includes a latch operative to synthesize a recovered data waveform in accordance with pairs of set and reset signals. Similarly, the inventive level detector includes a latch which utilizes set and reset signals to generate a level detection signal.

Differential high frequency level detector and data restoration circuit

A multiphase clock generator which exhibits frequency stability in the presence of power supply noise. The clock generator of the present invention includes a phase detector for generating a phase error signal in response to the phase difference between an input signal and a recovered clock signal. A phase-locked feedback loop is operative to synthesize a recovered clock signal in response to the phase error signal. Included within the feedback loop is a differential ring oscillator disposed to provide first and second phase-shifted output signals at first and second output ports. The addition of a combination network to the multiphase clock generator of the present invention allows a multiplied clock signal to be derived from an input signal. Specifically, the phase-locked feedback loop 18 included within the clock multiplier of the present invention provides a plurality of sequentially phase-shifted waveforms at a first multiple of the frequency of the input signal. The phase-shifted waveforms are then combined into the output clock signal at a second multiple of the frequency of the input clock signal.

Multi-phase clock generator and multiplier

A method and apparatus for predistorting digital signals so as to minimize radiation of harmonic signal energy during data transmission. The programmable waveshaping apparatus of the present invention is operative to predistort a binary encoded waveform to be transmitted over a transmission line. A pulse discriminator circuit is disposed to indicate the receipt of each pulse within an input sequence of short and long pulses included within the encoded waveform. Upon receipt of each short and long pulse an input logic network generates first and second sets of control signals, respectively. The logic network synthesizes the control signals based on information relating to sampled approximations of filtered versions of the short and long pulses. The inventive waveshaping apparatus further includes a programmable electrical source array for generating a sequence of line driving signals in accordance with each set of control signals. A transformer driver then pulses the transmission line in response to the driving signals in order to transmit information included within the encoded input sequence.

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Milpitas, CA, United States of America

Ramon S Co