Ncr Corporation

E-systems, Inc.

Ramon P Chambers

Robert S Gordy

David E Sanders

Cameron E Morrison

William H Mosley, Jr

Billy R Poston

A segmented, transversal correlator for use in a spread spectrum communications system accurately synchronizes to an incoming spread signal by passively searching for a particular section of a known reference PN code sequence. To achieve correlator lengths of greater than one data bit long, the correlator may comprise a plurality of correlation subsections, each including a loading register for storing a different section of the overall reference PN code sequence. A section of the PN code sequence is transferred into a circulating register in each subsection through a parallel transfer. The dynamic, circulating PN code sequence is then correlated against statically stored analog samples of the incoming spread signal. When the dynamic PN reference code sequence is aligned with the corresponding PN sequence in the analog samples, a correlation signal is produced and magnitude detected to form a signal which is applied to a summation circuit. The summation circuit receives the outputs of each of the correlator subsections and produces a correlation output signal for the entire correlator.

Transversal correlator

Frequency indication pulses are applied to comparison and feedback logic for the identification of a frequency in a selected frequency band. The comparison and feedback logic is part of an identification circuit that includes a main memory for storing representations of frequency values that is coupled to the comparison and feedback logic by data transfer gating. Control logic coupled to the data transfer gating and main memory provides shift pulses, clock pulses and control signals to sequence the operation of the main memory and comparison and feedback logic. Interval timing and control logic receives from the RF section of the compressive receiver a compare signal, a manual set signal and clock pulses to generate inhibit and enable signals for the comparison and feedback logic, and the control logic. When a comparison in the comparison and feedback logic between a received frequency indication pulse and a memory bit from the main memory indicates the presence of a new frequency, frequency value information, in the form of a sixteen bit data word, is transferred to interface logic and interface memory that encodes a digital word representing a specific frequency occurring within the time constrained subinterval. This digital word representation of a specific frequency is applied to an interface bus as frequency data available to the other sections of the compressive receiver.

Frequency identification circuit

An anti-jam PN sequence spread spectrum conferencing communication system is disclosed for simultaneously transmitting and receiving in a plurality of communications channels secure voice communications. All received messages are modulated with the same pseudo noise sequence and arrive at any given channel at random time states, wherein the messages are separated, separately processed and finally conferenced, using a technique based upon the correlation of the PN sequence and dependent upon the randomness of the epoch state of a given PN sequence coded with a message in relation to the other coded messages.

Spread spectrum conferencing communication system

A radio receiver is disclosed which measures the statistics of an interfering narrow band noise signal and from these statistics generates a function which when mixed at baseband with a data signal combined with the narrow band noise reduces the interfering effect of the noise signal. The interference eliminating function is generated by processing signals representing an approximation of the data, the covariance of the narrow band noise interference, the noise figure for the receiver and the amplitude of the data signal. As the function is generated it is input to a mixer together with the combined narrow band noise and data signal. Iterated processing improves the estimation for the noise statistics thereby improving the approximation for the resulting data signal. This further enhances the solution for the noise elimination function thereby still further improving the desired data signal, thus creating a positive improving feedback loop.

Adaptive narrow band noise estimator/suppressor radio receiver

The carrier suppression circuit of the present invention is utilized to minimize electrical imbalances within double-balanced mixers. The circuit operates upon a modulating signal, having at least two states so as to adjust the dwell time that the signal stays in a particular state to counteract the effects of electrical imbalance within the mixer. Minimization of the electrical imbalance provides a greater suppression of the carrier signal which, in turn, improves the quality of the signal both at the transmitter and at the receiver.

Compensation circuit for an electrical signal mixer

A four phase to two phase correlator is incorporated within the demodulator section of a spread spectrum modem to process a received RF signal modulated by a transmitted PN code and a digital data signal. The correlator includes a first modulator for combining the channel 1 and channel 2 R code signals with the received RF input signal to generate a first channel 1 RF signal and a first channel 2 RF signal. The first channel 1 RF signal is modulated by the transmitted PN code signal, the channel 1 R code signal and the digital data signal. The first channel 2 RF signal is modulated by the transmitted PN code signal, the channel 2 R code signal and the digital data signal. A second modulator combines the channel 1 and channel 2 PN code signals and the channel 1 and channel 2 R code signals with a first unmodulated RF signal to generate a second channel 1 RF signal which is modulated by the channel 1 PN code signal and by the channel 1 R code signal, and a second channel 2 RF signal which is modulated by the channel 2 PN code signal by the channel 2 R code signal. A third modulator combines both channels of the first and second RF signals to generate a third RF signal which is modulated only by the digital data signal.

Four phase to two phase correlator

A correlator error detector generates a first repeating digital pseudo noise code signal which is compared in a correlator to a second signal generated by the error detector with the second signal having the same pseudo noise code but with a noise signal intentionally added. The error detector measures the capability of the correlator to correlate the first signal with the second signal under varying noise conditions. Errors produced by the correlator are counted, and classified as being either missed correlation outputs or false correlation outputs.

Transversal correlator error detector

The detector of the present invention includes a first and a second signal channel each of which is adapted to receive a spread spectrum signal, or any other similar type multi-modulated carrier signal. In the preferred embodiment of the invention, the first signal channel is provided with a correlator for partially demodulating the received signal, as to one modulation signal component, with a demodulation signal derived from the second signal channel. The first signal channel is also provided with an additional correlator for demodulating the partially demodulated signal as to another modulation component. The second signal channel is comprised of a means for generating a dithered demodulation signal which signal is driven into synchronization with a corresponding modulation signal component in the received signal so as to enable the accurate generation of the demodulation signal utilized by the first signal channel.

Spread spectrum detector

An offset error correction circuit for improved reception of signals by compensating for any offset error voltage produced by a phase detector in the absence of an input signal to the detector. The error correction circuit translates the offset error voltage into a digital value and stores that value in a counter. When a PSK signal is applied to the circuit, the error correction circuit subtracts the stored value of the offset error voltage from the output of the phase detector which compensates for the offset error. The compensation for the offset error provides an improved signal to noise ratio.

Offset correction circuit for phase detectors

Apparatus and method are provided to discriminate between true locking of a phase-locked loop on the main lobe of an information signal, and false locking on a side lobe thereof. The energy in the locked signal is sensed and compared with the signal energy at fixed frequency increments, preferably twice the bit clock rate frequency, above and below the lock frequency. A greater energy content at the increment frequencies than at the locked frequency indicates a false lock condition and is used to inhibit the loop from entering a locked mode.

Apparatus and method for inhibiting false locking of a phase-locked loop

A digitized automatic gain controlled amplifier and gain hysteresis circuit is disclosed for preserving a low frequency, low level modulation at the output of an AGC amplifier while also providing for rapid correction of amplifier gain for large variations in the amplifier input signal level. The described amplifier is particularly adapted to satellite communications systems in which ionospheric changes produce rapid power fades and wherein satellite tracking is accomplished by dithering a high-gain antenna on the satellite to produce a low-frequency power amplitude control signal at the input to the AGC amplifier, which control signal is allowed to pass through to a control system while the larger input signal variations are gain-controlled out.

Digitized AGC amplifier with gain hysteresis circuit

A high speed divide-by-two circuit operable in the 400 to 500 MHz frequency range comprising a pair of transistors having their emitters connected in common to an input circuit and their bases and collectors cross-coupled by a pair of capacitors. The collectors of the transistors are also coupled together by a single inductor.

High speed divide-by-two circuit

In the present invention a received DPSK signal is sampled at times corresponding to a peak signal to noise ratio and the sample of signal is passed to a circulating memory. A phase detector is connected to receive the DPSK signal and the sample of signal circulating in the memory to provide an output signal indicative of the phase relationships between the received DPSK signal and the circulating sample signal. A sampling means samples the output signal from the phase detector at the correct bit time, to provide a signal which is a function of the differential phase between adjacent bits of the received DPSK signal.

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Clearwater, FL, United States of America

Ramon P Chambers