Intel Corporation

Ramon Matas

Anshuman Thakur

Roger Gramunt

Ramacharan Sundararaman

Alexey Suprun

Steven Chang

Chung-Lun Chan

Benjamin C Chaffin

Rammohan Padmanabhan

Aditya Kesiraju

Neal S Moyer

Robert F Netting

Matthew G Smith

Jay S Lawlor

Jesus Corbal

Jonathan Cannon Hall

Julio Gago

Vikram S Sundaram

Gerardo A Fernandez

Michael S Yang

An instruction in a first cache line may be identified and an address associated with the instruction may be determined. The address may be determined to cross a cache line boundary associated with the first cache line and a second cache line. In response to determining that the address crosses the cache line boundary, the instruction may be adjusted based on a portion of the address included in the first cache line and a second instruction may be created based on a portion of the address included in the second cache line. The second instruction may be injected into an instruction pipeline after the adjusted instruction.

Resolving memory accesses crossing cache line boundaries

A processor includes a logic for stateless capture of data linear addresses (DLA) during precise event based sampling (PEBS) for an out-of-order execution engine. The engine may include a PEBS unit with logic to increment a counter each time an instance of a designated micro-op is retired a reorder buffer, capture output DLA referenced by an instance of the micro-op that executes after the counter overflows, set a captured bit associated with a reorder buffer identifier for the instance of the micro-op, and store a PEBS record in a debug storage when the instance of the micro-op is retired from the reorder buffer. The designated micro-op references a DLA of a memory accessible to the processor.

Stateless capture of data linear addresses during precise event based sampling

Methods, systems, and apparatuses relating to sharing translation lookaside buffer entries are described. In one embodiment, a processor includes one or more cores to execute a plurality of threads, a translation lookaside buffer comprising a plurality of entries, each entry comprising a virtual address to physical address translation and a plurality of bit positions, and each set bit of the plurality of bit positions in each entry indicating that the virtual address to physical address translation is valid for a respective thread of the plurality of threads, and a memory management circuit to clear all set bits for a thread by asserting a reset command to a respective reset port of the translation lookaside buffer for the thread, wherein the translation lookaside buffer comprises a separate reset port for each of the plurality of threads.

Apparatuses, methods, and systems to share translation lookaside buffer entries

An apparatus and method for performing an efficient scatter operation. For example, one embodiment of a processor comprises: an allocator unit to receive a scatter operation comprising a number of data elements and responsively allocate resources to execute the scatter operation; a memory execution cluster comprising at least a portion of the resources to execute the scatter operation, the resources including one or more store data buffers and one or more store address buffers; and a senior store pipeline to transfer store data elements from the store data buffers to system memory using addresses from the store address buffers prior to retirement of the scatter operation.

Method and apparatus for performing an efficient scatter

In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.

Scalable event handling in multi-threaded processor cores

Exemplary aspects are directed toward resolving fault suppression in hardware, which at the same time does not incur a performance hit. For example, when multiple instructions are executing simultaneously, a mask can specify which elements need not be executed. If the mask is disabled, those elements do not need to be executed. A determination is then made as to whether a fault happens in one of the elements that have been disabled. If there is a fault in one of the elements that has been disabled, a state machine re-fetches the instructions in a special mode. More specifically, the state machine determines if the fault is on a disabled element, and if the fault is on a disabled element, then the state machine specifies that the fault should be ignored. If during the first execution there was no mask, if there is an error present during execution, then the element is re-run with the mask to see if the error is a 'real' fault.

Memory fault suppression via re-execution and hardware FSM

Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.

Boot strap processor assignment for a multi-core processing unit

An initialization core may include reset logic that may detect a global reset signal (GRS). The initialization core may generate one or more packets that enable communication with the cores. The initialization core may send reset packets to each of the cores that instruct the cores to perform a reset. In some embodiments, the reset command may power-off the cores. The initialization core may then transmit unreset packets to each of the cores that instruct the cores to perform an unreset and power-on the cores. In some embodiments, the cores may resume operation automatically without receipt of the unreset packet. The transmission of the packets may be staggered (staged) to control the power-on of the processor and enable the processor unit to more slowly increase its power state.

Reset of multi-core processing system

Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.

Advanced programmable interrupt controller identifier (APIC ID) assignment for a multi-core processing unit

This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using packets. An initialization core may include reset logic that may read initialization and configuration vectors from a centralized storage location, which may be on a die containing the processing cores (e.g., a fuse, etc.), off the die (e.g., in volatile memory, flash memory, etc.), or a combination of both. The initialization core may then generate packets to transmit the initialization and configuration vectors to processing cores that await initialization (e.g., following a reset). In some instances, the initialization and configuration vector information may be shared by two or more cores of a same type.

Initialization of multi-core processing system

This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset.

Reset of processing core in multi-core processing system

In one embodiment, a processor includes an address generation unit having a memory context logic to determine whether a memory context identifier associated with an address of a memory access request corresponds to an agent memory context identifier for the processor, and to handle the memory address request based on the determination.

Growing community of inventors

Portland, OR, United States of America

Ramon Matas