International Business Machines Corporation

Ramon M Bertran

Alper Buyuktosunoglu

Pradip Bose

Timothy John Slegel

Jingwen Leng

Timothy J Siegel

Methods and systems for executing an application includes executing an epoch of the application using a predicted minimum operational voltage that is based on a previous epoch of the application if the application is in a stable phase and using a nominal safe voltage if the application is in an unstable phase.

Predicting voltage guardband and operating at a safe limit

One aspect is an analysis system that includes a processor operably coupled to a memory and configured to perform a method. The method includes defining a set of workloads for a targeted multi-core computer system based on a plurality of metrics of interest to profile. A plurality of workload-to-core mappings is generated for the workloads on the targeted multi-core computer system. The workloads run on the targeted multi-core computer system based on the workload-to-core mappings to produce a mapping of the workloads to the metrics of interest as experimental data. A statistical analysis is applied on the experimental data to define a plurality of metric profiles for the targeted multi-core computer system.

Computer system performance analyzer

Methods and systems for executing an application includes predicting a minimum operational voltage for a next epoch of an application based on performance counters collected in a previous epoch of the application. The next epoch of the application is executed using the predicted minimum operational voltage if the application is in a stable phase and using a nominal safe voltage if the application is in an unstable phase.

One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted complex-instruction set computer (CISC) processor to generate an instruction set profile for each CISC architectural instruction variant of the instruction set architecture. A combination of instruction sequences for the targeted CISC processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted CISC processor. Performance of the targeted CISC processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. The targeted CISC processor is stress tested based on executing at least one of the instruction sequences identified as most closely aligning with the desired stressmark type.

Generation and application of stressmarks in a computer system

An aspect includes pruning a design space when generating a maximum power stressmark. A multi-stage design space search process is performed. Each stage includes calculating a number of instructions per cycle (IPC) for each instruction sequence in a set of instruction sequences that place a power stress on a system under analysis, removing one or more of the instruction sequences having an IPC lower than a pruning threshold from the set, evaluating at least one power metric of the remaining instruction sequences in the set, removing one or more of the instruction sequences having at least one power metric evaluated outside of one or more pruning ranges from the set, and passing the remaining instruction sequences in the set to a next stage. A maximum power stressmark is generated based on the evaluating of the at least one power metric from a final stage.

Space reduction in processor stressmark generation

One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted complex-instruction set computer (CISC) processor to generate an instruction set profile for each CISC architectural instruction variant of the instruction set architecture. A combination of instruction sequences for the targeted CISC processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted CISC processor. Performance of the targeted CISC processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. One of the instruction sequences is identified as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.

Monitoring is performed for a requested change in a number of active processor cores within a multi-core processor. A current power level setting of the multi-core processor is checked based on the requested change in the number of active processor cores. A targeted power level setting associated with the requested change in the number of active processor cores is determined, where the targeted power level setting incorporates a worst case noise level margin defined on an active processor core basis. The current power level setting is adjusted to align with the targeted power level based on determining that the current power level setting fails to meet the targeted power level within a threshold band.

Idle-aware margin adaption

One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted processor to generate an instruction set profile for each instruction of the instruction set architecture. A combination of instruction sequences for the targeted processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted processor. Performance of the targeted processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. One of the instruction sequences is identified as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.

Processor stressmarks generation

A time-of-day (TOD) clock is leveraged to provide a high-resolution measure of the real time that is suitable for the indication of date and time to perform cycle-level thread synchronization. A time-of-day value provided by the time-of-day clock is used in a spin lock, along with a configurable mask, to meet a specified condition. The condition is met at regular time intervals and at the same time for all the hardware threads to be synchronized. When the condition is met and synchronization is reached, execution of the threads continues ensuring that the activity generated on each thread is in synchronization.

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Manhattan, NY, United States of America

Ramon M Bertran