International Business Machines Corporation

Ramon Bertran Monfort

Alper Buyuktosunoglu

Pradip Bose

Tobias Webel

Preetham M Lobo

Karthik V Swaminathan

Pradeep Bhadravati Parashurama

Giora Biran

Phillip John Restle

Chen-Yong Cher

Christos Vezyrtzis

Pierce I-Jen Chuang

Jingwen Leng

Hans Mikael Jacobson

Augusto Javier Vega

Srinivas Bangalore Purushotham

Nandhini Chandramoorthy

William J Song

Liang Wang

Hubertus Franke

Martin Recktenwald

Nitish Jindal

Archit Kapoor

Calvin Bulla

A computer-implemented method for detecting n-level slopes for a voltage level in a processor, wherein n is greater than 1, includes monitoring a voltage in a processor for a voltage level corresponding to a predefined first edge, and monitoring for a voltage level corresponding to a predefined second edge within a first count limit from detection of the predefined first edge. In response to detecting the predefined second edge within the first count limit, the computer-implemented method includes monitoring for a voltage level corresponding to a predefined third edge within a second count limit from detection of the predefined second edge, and in response to detecting the predefined third edge within the second count limit, determining whether to adjust a power applied to the processor based on the monitored voltage levels.

Voltage droop and overshoot management using non-linear slope detection

Embodiments relate to a system, program product, and method for mitigating voltage overshoot in one or more cores in a multicore processing device including a plurality of cores. The method includes determining, in real-time, an indication of power consumption within each core of the one or more cores. The method also includes determining, through the indication of power consumption, a voltage overshoot condition in the one or more cores. The method further includes increasing, for the one or more cores, a power demand thereof. The method also includes increasing, subject to the increasing the power demand, power delivery to the one or more cores, thereby at least arresting the rate of increase of the voltage overshoot.

Voltage overshoot management

A computer-implemented method, a computer system and a computer program product customize generation and application of stress test conditions in a processor core. The method includes receiving a workload at the processor core, where the workload includes a plurality of instructions and the processor core comprises a plurality of macros. The method also includes obtaining macro performance data for each macro in the plurality of macros from the processor core. The method further includes determining a switching activity level for each macro in the plurality of macros when each instruction in the plurality of instructions is run based on the macro performance data. Lastly, the method includes generating a stressmark comprising the plurality of instructions in the workload, where the stressmark is associated with a macro in the plurality of macros when the switching activity level for the macro is above a minimum threshold.

Customizing stressmarks in a computer system

Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

Proactive voltage droop reduction and/or mitigation in a processor core

Embodiments relate to a system, program product, and method for proactively initiating throttle action on one or more cores in a multicore processing device to mitigate voltage droop therein. The method includes determining, in real-time, an indication of stall events within the core and determining one or more resolutions of the stall events. The method also includes determining, in real-time, a timing margin value for the core and predicting inducement of a voltage droop on the core. The method further includes integrating the resolutions of the stall events and the timing margin value for the core, determining, subject to the predicting, a throttle action for the core, and executing the throttle action on the core.

Voltage droop management through microarchitectural stall events

Embodiments for generating representative microbenchmarks in a computing environment are provided. One or more tracing points may be selected in a target application. Executed instructions and used data of the target application may be dynamically traced according to the one or more tracing points according to a tracing plan. Tracing information of the dynamic tracing may be replicated in an actual computing environment and a simulated computing environment.

Generating representative microbenchmarks

Embodiments are disclosed for managing voltage droop. The techniques include performing a first determination that a timing margin is less than a first threshold. The techniques also include performing a second determination that an increase in processor activity exceeds a second threshold. Additionally, the techniques include determining that a voltage droop is indicated based on the first determination and the second determination. Further, the techniques include signaling a plurality of throttling circuits for a corresponding plurality of cores of a computer processor to actuate.

Mitigating voltage droop

A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (V), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.

Reliability-aware runtime optimal processor configuration

Applications on different processing elements have different characteristics such as latency versus bandwidth sensitivity, memory level parallelism, different memory access patterns and the like. Interference between applications due to contention at different sources leads to different effects on performance and is quantified. A method for contention-aware resource provisioning in heterogeneous processors includes receiving stand-alone performance statistics for each processing element for a given application. Multi-core performance slowdown can be computed from the received stand-alone performance statistics. When a request to provision an application on the heterogeneous processors is received, application performance requirements of the application can be determined and a bandwidth for the application can be provisioned based on the application performance requirements and the computed multi-core performance slowdown parameter.

Contention-aware resource provisioning in heterogeneous processors

Preferred embodiments of systems and methods are disclosed to reduce a minimal working voltage, Vmin, and/or increase the frequency of Vmin while executing multithreaded computer programs with better reliability, efficiency, and performance. A computer complier complies multiple copies of high-level code, each with different a different set of resource allocators so system resources are allocated during simultaneous execution of multiple threads in a way that allows reducing Vmin at a given reference voltage frequency and/or increasing the frequency of Vmin at a given Vmin value.

Reducing minimum operating voltage through heterogeneous codes

An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.

Optimization of application workflow in mobile embedded devices

A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures. The method additionally includes performing an error recovery operation that replays the set of operations by the original co-processor and the redundant co-processor, responsive to identifying a mismatch between the respective execution signatures.

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New York, NY, United States of America

Ramon Bertran Monfort