Motorola Corporation

Ramnath Venkatraman

Robert W Fiordalice

T P Ong

Elizabeth J Weitzman

Gregor Braeckelmann

Avgerinos V Gelatos

Suresh Venkatesan

Olubunmi O Adetutu

Douglas Michael Reber

Alexander Barr

Stanley Michael Filipiak

Rabiul Islam

Kevin D Lucas

Sam S Garcia

Matthew Thomas Herrick

Dean J Denning

Cindy Reidsema Simpson

Ajay Jain

Stuart E Greer

Jeffrey T Wetzel

Brian George Anthony

David Clegg

John Mendonca

Cristiano Capasso

Stephen R Crown

Rebecca G Cole

Gregory Norman Hamilton

Tze W Poon

An interconnect overlies a semiconductor device substrate ( ). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer ( ) overlies the conductive barrier layer and the passivation layer ( ) has an opening that exposes portions of the conductive barrier layer ( ). In an alternate embodiment a passivation layer ( ) overlies the interconnect, the passivation layer ( ) has an opening ( ) that exposes the interconnect and a conductive barrier layer ( ) overlies the interconnect within the opening ( ).

Method of forming semiconductor device including interconnect barrier layers

An interconnect (,) is formed overlying a substrate (,). In one embodiment, an adhesion/barrier layer (,), a copper-alloy seed layer (,), and a copper film (,) are deposited overlying the substrate (,), and the substrate (,) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (,), a seed layer (,), a conductive film (,), and a copper-alloy capping film (,) are deposited over the substrate (,) to form an interconnect (,). The deposition and annealing steps can be performed on a common processing platform.

Method for forming a semiconductor device

In one embodiment, a copper interconnect structure is formed by depositing a dielectric layer (,) on a semiconductor substrate (,). The dielectric layer (,) is then patterned to form interconnect openings (,). A layer of copper (,) is then formed within the interconnect openings (,). A portion of the copper layer (,) is then removed to form copper interconnects (,) within the interconnect openings (,). A copper barrier layer (,) is then formed overlying the copper interconnects (,). Adhesion between the copper barrier layer (,) and the copper interconnects (,) is improved by exposing the exposed surface of the copper interconnects (,) to a plasma generated using only ammonia as a source gas.

Copper interconnect structure and method of formation

A method of forming a semiconductor device by first providing a substrate in a processing chamber. The substrate has an insulating layer and an opening in the insulating layer. A copper barrier layer is formed on the insulating layer and in the opening by providing a plurality of refractory metal atoms and a plurality of silicon atoms in the processing chamber. The atoms are ionized by applying a first bias to the atoms to form a plasma. The substrate is then biased by a first stage bias followed by a second stage bias to accelerate the plasma to the substrate to form the copper barrier layer, where the first stage bias is less than the second stage bias. The copper-containing metal is then deposited on the copper barrier layer over the insulating layer and in the opening. The present invention further includes a semiconductor device formed by the above method.

Semiconductor device with a copper barrier layer and formation thereof

A process for fabrication of a multilevel interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to fill the via opening (14) at the bottom of an interconnect channel (24). Selective deposition is enhanced by the use of a nucleation layer (20) which is formed on the bottom of the via opening, without being formed on the sidewalls, by use of directional deposition technique such as inductively coupled plasma (ICP) deposition. Nucleation layer (20) eases requirements of a cleaning operation prior to selective deposition and provides a surface from which void-free selective growth can occur.

Process for fabricating a multilevel interconnect

An interconnect structure (10) is formed by filling a dual damascene structure (12) with conductive material. A barrier layer (13) is formed to serve as a seed layer and to prevent the out diffusion of copper. A first conductive layer (14) is formed to fill a first portion (21) of the damascene structure (12). A second conductive layer (16) is then formed to complete the filling of a second portion (22) of the damascene structure. A polishing process is then used to remove any excess material.

Method of forming an interconnect structure

A process for fabrication of a metallized interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to at least partially fill the via opening (14) at the bottom of an interconnect channel (24). An adhesion layer (36) is deposited to overlie the aluminum layer (34) within the via opening (14), and a second aluminum layer (38) is blanket deposited and planarized to form the inlaid interconnect (42) in the interconnect channel (24).

Process for fabricating a metallized interconnect

An interconnect structure (10) is formed by filling a dual damascene structure (12) with conductive material. A barrier layer (13) is formed to serve as a seed layer and to prevent the out-diffusion of copper. A discontinuous film (30) of islands (41) is used to dope the interconnect structure (10)with copper. A conductive layer (14) is formed to fill a first portion (21) and a second portion (22) of the damascene structure (12). An anneal step is performed to diffuse the copper into the conductive layer (14).

Method of alloying an interconnect structure with copper

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Austin, TX, United States of America

Ramnath Venkatraman