Qualcomm Incorporated

Apple Inc.

Ramkumar Srinivasan

Vedaraman Geetha

Keith Robert Pflederer

Amit Kumar

Vikas Kumar Sinha

Frederick B Fisher

Bin Lin

Christopher T Weaver

Ashwini Simha

Varun Palivela

Gerard Williams

In one aspect, a delta prefetcher disclosed herein bases its predictions on both past memory accesses and predictively prefetched memory accesses. More specifically, the delta prefetcher disclosed herein bases its prediction on both the difference or 'delta' between memory addresses of data previously fetched from memory and the difference or “delta” between addresses of data predictively fetched from memory. The delta prefetcher tracks the delta memory accesses by utilizing two distinctive tables. The fetch table tracks the memory deltas for each memory operation, such as a LOAD or STORE instruction, that the CPU has executed. The delta table predicts the next memory address to prefetch based on the last prefetched memory accesses.

System for prefetching data into a cache

A processor-based system for allocating a higher-level cache line in a higher-level cache memory in response to an eviction request of a lower-level cache line is disclosed. The processor-based system determines whether the cache line is opportunistic, sets an opportunistic indicator to indicate that the lower-level cache line is opportunistic, and communicates the lower-level cache line and the opportunistic indicator. The processor-based system determines, based on the opportunistic indicator of the lower-level cache line, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line. In response, the processor-based system replaces the higher-level cache line in the higher-level cache memory with the lower-level cache line and associates the opportunistic indicator with the lower-level cache line in the higher-level cache memory.

Processor-based system for allocating cache lines to a higher-level cache memory

Resources of an electronic device are partitioned into a plurality of resource portions to be utilized by a plurality of clients. Each resource portion is assigned to a respective client, has a respective partition identifier (ID), and corresponds to a plurality memory bandwidth usage states tracked for a plurality of memory blocks. For each resource portion, each of the memory bandwidth usage states is associated with a respective memory block and indicates at least how much of a memory access bandwidth assigned to the respective partition ID to access the respective memory block is used. A usage level is determined for each resource partition based on the memory bandwidth usage states, and applied to adjust a credit count. When the credit count is adjusted beyond a request issue threshold, a next data access request is issued from a memory access request queue for the respective partition ID.

Methods and systems for memory bandwidth control

Resources of an electronic device are partitioned into a plurality of resource portions to be utilized by a plurality of clients. Each resource portion is assigned to a respective client, has a respective partition identifier (ID), and corresponds to a plurality of memory bandwidth usage states tracked for a plurality of memory blocks. For each resource portion, each of the memory bandwidth usage states is associated with a respective memory block and indicates at least how much of a memory access bandwidth assigned to the respective partition ID to access the respective memory block is used. A usage level is determined for each resource partition based on the memory bandwidth usage states, and applied to adjust a credit count. When the credit count is adjusted beyond a request issue threshold, a next data access request is issued from a memory access request queue for the respective partition ID.

Performance counters provided in a graphics processor unit (GPU) are used to provide values used to make a determination of GPU activity so that power management can be exercised. In preferred embodiments counter values relating to computation unit idle times, computation unit stall times, DRAM bandwidth and computation unit stall times due to a sampler wait are utilized to determine performance level. If performance is above a minimum level but the GPU is above certain idleness determinations provided by those values, the GPU can have portions powered down to reduce power consumption while not having a noticeable effect on operations. Based on the various counter values, portions of the GPU can be turned off or disabled to reduce power consumption without having a noticeable effect on perceived GPU performance.

Growing community of inventors

San Jose, CA, United States of America

Ramkumar Srinivasan