Qualcomm Incorporated

Ramkumar Sivakumar

Vijayakumar Dhanasekaran

Kshitij Yadav

Xinwang Zhang

Sherif Galal

Jingxue Lu

Khaled Mahmoud Abdelfattah Aly

Dongyang Tang

Jorge Garcia

Subbarao Surendra Chakkirala

Qubo Zhou

Pradeep Charles Silva

Wenchang Huang

Hanil Lee

A transmission line includes an equalization circuit. The equalization circuit is a second-order equalization circuit having a first loop at a gain element and a second loop at the gain element. The first loop may include a first compensation capacitor, and the second loop may include a second compensation capacitor and a resistor. The second order equalization circuit may allow for improved performance with respect to gain as well as reduced power usage.

Second-order equalizer for high-speed data lines

A differential ESD circuit is provided for protecting a pair of differential terminals of an integrated circuit from electrostatic shock. A first diode couples between a first terminal in the pair of differential terminals and a first resistor that couples to a voltage node of the integrated circuit. Similarly, a second diode couples between a second terminal in the pair of differential terminals and a second resistor that couples to the voltage node of the integrated circuit. The first and second resistors isolate the first and second terminals from a capacitive loading that would otherwise exist from the first and second diodes.

Fully differential ESD circuit for high-frequency applications

A voltage comparator includes a boosting circuit that is configured to boost a direct current (DC) bias of the comparator. The boosting circuit includes transistors that are different in size, a larger one of the transistors being configured to add a portion of boosting current to a bias current.

Boosting circuits and methods for comparator circuits

Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.

Voltage-to-current architecture and error

A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.

Area efficient level translating trigger circuit for electrostatic discharge events

Voltage-to-current architecture and error correction schemes

A power amplifier provides reduction of click and pop in audio applications. The power amplifier includes a first amplifier and an auxiliary amplifier. The auxiliary amplifier is used to ramp the power amplifier output from ground to an offset voltage to reduce the 'click and pop' sound. The first amplifier and the auxiliary amplifier having a shared feedback loop. An output of the first amplifier and an output of the auxiliary amplifier may be switchably coupled to the shared feedback loop. A wave generator controls a switch to couple the first amplifier output or the auxiliary amplifier output to the shared feedback loop.

Audio power amplifier for reduced click and pop (CnP)

Certain aspects of the present disclosure generally relate to a sampling network of a switched-capacitor integrator and a clocking scheme associated therewith, which may be used in an analog-to-digital converter (ADC), for example. The integrator generally includes five sets of switches which allow for a decreased switching frequency (e.g., halved) at an input stage of the integrator compared to conventional double sampling networks. As a result, the input impedance of the integrator may be increased (e.g., doubled), resulting in lower power consumption and reduced strain on driving circuitry.

Sampling network and clocking scheme for a switched-capacitor integrator

An apparatus for supplying power to a load. The apparatus including a plurality of sources to provide charge, and a controller adapted to control a transfer of charge from the sources to the load at distinct times. The controller may control the transfer of charge based on variation of an ambient condition or a manufacturing process. The controller may control the transfer of charge to generate a defined voltage across the load. The apparatus may include a regulator adapted to regulate a voltage across the load. The regulator may regulate the voltage across the load in a defined timing relationship with the transfer of charge from the sources to the load.

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San Diego, CA, United States of America

Ramkumar Sivakumar