Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Ramkumar Ramamurthy

Ramanathan Muthiah

Narendhiran Chinnaanangur Ravimohan

Balaji Thraksha Venkataramanan

Muralitharan Jayaraman

Lovish Singla

Yehuda Hahn

Dinesh Kumar Agarwal

Vijay Sivasankaran

Raghavendra Gopalakrishnan

Arun Thandapani

Balakumar Rajendran

Shaheed Nehal A

Kalpit Bordia

Meenakshi C

Pradeep Sreedhar

Rohit Sathyanarayan

Anamika Choudhary

Satya Kesav Gundabathula

Bhavya Krishna

Bhanushankar Doni Gurudath

Prashanth Reddy Enukonda

Ravi Gaja

Bhagyashankar Muthu Kumaresan

Sachin Krishna Kudva

Ashim Ranjan Saikia

A data storage device and method for host-assisted deferred defragmentation and system handling are provided. In one embodiment, the data storage device comprises a memory and a controller. The controller is configured to receive, from a host, a plurality of write commands and a grouping identifier associated with the plurality of write commands, wherein the plurality of write commands comprise a plurality of non-sequential logical block addresses and a plurality of sequential segments of a file; and in response to the grouping identifier being associated with the plurality of write commands, execute the plurality of write commands by storing the plurality of sequential segments of the file sequentially in the memory even though the logical block addresses associated with the segments of the file are non-sequential. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Data storage device and method for host-assisted deferred defragmentation and system handling

Various embodiments of this disclosure are directed to a mixed digital and analog domain approach to computational storage or memory applications. The mixed approach enables certain compute operations to be advantageously performed in the analog domain, achieving power saving. In some embodiments, an analog compute core is implemented based on a first set of memory elements that are made available with a second set of memory elements for digital data storage. A controller coupled to both sets of memory elements is able to selectively direct computational tasks to either the analog compute core or a digital processor coupled with the controller, based on one or more parameters including power, precision, and workload. In certain embodiments involving neural network tasks, the controller is configured to route certain tasks to the analog compute core based on neural network based factors such as network layer positioning and input signal type.

Adaptive mixed digital and analog computational storage systems

A storage device performs a format operation for host devices using different format times and commands configurations. When a controller on the storage device receives an erase command from a host device, the controller determines the format time and a chunk size associated with data in the erase command. The controller executes a first format operation scheme, a second format operation scheme, or a third format operation scheme to perform an erase operation on the data in the erase command within the format time. The controller halts execution of the erase operation and returns operation to the host device when the format time expires.

Time bound partial format operation in a storage device

In solid state memory devices, garbage collection can be a bottleneck in meeting stringent performance requirements of certain hosts that generate a relatively-large amount of data (e.g., hosts that generate video data). With such hosts, the performance drop caused by background garbage collection can result in video recording failures. The memory device and method presented herein performs background operations in such a way as to enhance sustained performance. In general, a counter is maintained that reflects an amount of memory written to by a host, as well as an amount of memory freed by garbage collection operations. Each step of a garbage collection operation can be performed in response to a value of the counter being greater than a threshold for the step such that there is a balance between memory written and memory freed.

Data storage device with balanced background operations and method therefor

A data storage device and method for enabling metadata-based seek points for media access are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to identify a plurality of frames in video data that differ from surrounding frames by more than a threshold amount; store identifiers of the plurality of frames in the memory; and send the identifiers to the host to enable quick playback of the video data by the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Data storage device and method for enabling metadata-based seek points for media access

A storage system and method for device-determined, application-specific dynamic command clustering are provided. In one embodiment, the storage system comprises a memory and a controller. The controller is configured to analyze commands received from a host to detect a pattern of a plurality of commands; inform the host of the pattern; receive, from the host, a single command comprising an identifier associated with the plurality of commands; and in response to receiving the single command from the host, executing the plurality of commands. Other embodiments are provided.

Storage system and method for device-determined, application-specific dynamic command clustering

Example storage systems, storage devices, and methods provide proactive management of storage operations to, for example, beneficially minimize bottlenecking, latency, and other issues. An example system has a storage pool with a first storage device and a second storage device, and a processor configured to generate a storage request including a storage command, include a command processing time constraint in the storage request, send the storage request to the first storage device, and receive, from the first storage device, a proactive response including an estimation for an execution of the storage command by the first storage device based on the command processing time constraint. The processor may then select a fallback mechanism for executing the storage command based on the proactive response.

Proactive storage operation management

Apparatuses and techniques are described for more efficiently allocating blocks of data in a memory device. The number of dedicated single-level cell (SLC) blocks which are allocated at the time of manufacture of a memory device can be reduced by transitioning a portion of the multi-level cell (MLC) blocks to an SLC mode at various times in the lifetime of the memory device. In one approach, separate counts are maintained for an MLC block in the SLC and MLC modes. The separate counts can be used to select an MLC block to transition to the SLC mode, or to select an MLC block to program. In another approach, a single count is maintained, where the SLC cycles are weighted less heavily than the MLC cycles.

Yield improvement through block budget optimization by using a transient pool of multi-level blocks

A storage system and method for enabling host-driven regional performance in memory are provided. In one embodiment, a method is provided comprising receiving a directive from a host device as to a preferred logical region of a non-volatile memory in a storage system; and based on the directive, modifying a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in a volatile memory of the storage system. Other embodiments are provided, such as modifying a garbage collection policy of the storage system based on information from the host device regarding a preferred logical region of the memory.

Storage system and method for enabling host-driven regional performance in memory

A storage system, host, and method for storage system calibration are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: determine a pattern of host writes to the memory; determine whether the pattern of host writes matches a granularity of a logical-to-physical address map used by the storage system; and in response to determining that the pattern of host writes does not match the granularity of the logical-to-physical address map used by the storage system, change the granularity of the logical-to-physical address map used by the storage system. In another embodiment, the storage system calibration is done by host directive. Other embodiments are provided.

Storage system and method for storage system calibration

Host and method for storage system calibration

An apparatus is provided that includes a non-volatile memory and a memory controller coupled to the non-volatile memory. The memory controller is configured to access a global address table (GAT) that maps logical addresses of a host to physical addresses of the non-volatile memory, receive a request from the host to write first data to the non-volatile memory, determine that the first data comprises fragmented data that are not aligned to a minimum write unit of the non-volatile memory, and create an unaligned GAT page, wherein the unaligned GAT page comprises a logical-to-physical mapping for the first data.

Flash translation layer table for unaligned host writes

Apparatus, systems, methods, and computer program products for buffering storage device data in a host memory buffer (HMB) are presented. A non-volatile memory and a controller are in communication with a non-volatile memory. A controller is configured to receive an input/output (I/O) operation including data. A controller is configured to transmit at least a portion of data to an HMB of a host device separate from a non-volatile memory and a controller for storage until a trigger event occurs.

Buffering storage device data in a host memory buffer

Apparatuses, systems, methods, and computer program products for streamed program commands with periodic garbage collection are disclosed. A controller is configured to set up a data path between the controller and a memory device to initialize an open mode. A controller is configured to perform a plurality of program operations on a memory device in an open mode using a same set up data path. A controller is configured to, in response to exiting an open mode, perform a garbage collection operation on a memory device.

Streamed program commands with periodic garbage collection

One or more control circuits of a storage system are configured to consolidate the sensing of pre-pad and/or post-pad data for one unaligned write command with the transferring of previously sensed pre-pad and/or post-pad data for another unaligned write command. By consolidating the sensing and transferring, considerable time is saved when programming data for a set of two or more unaligned write commands. Also, in one aspect, a single programming operation is performed for multiple unaligned write commands. Some conventional solutions may need to perform a programming operation for each unaligned write command. Hence, considerable programming time is saved by the storage system. Moreover, write amplification may be reduced by the storage system.

Growing community of inventors

Bengaluru, India

Ramkumar Ramamurthy