Intel Corporation

Ramkumar Nagappan

Jonathan M Eastep

Alan Beecher Kyker

Richard J Greco

Federico Ardanaz

Muralidhar Rajappa

Manasi Deval

Cong Li

Anjaneya Reddy Chagam Reddy

Eric K Mann

David Wescott

Raed Kanjo

Jim Daubert

Alan G Gara

Devadatta V Bodas

James W Alexander

Robin A Steinbrecher

Andy Hoffman

Janusz Jurski

Mariusz Oriol

Tozer J Bandorawalla

Christopher M Cantalupo

Piotr Sawicki

Shankar Krishnan

Steve S Sylvester

Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

Systems and methods for synergistic software-hardware power budget management

An apparatus is provided which comprises: a first circuitry to receive a measurement of a first temperature of a section of a computing device during a first loading condition of the computing device, and to receive a measurement of a second temperature of the section of the computing device during a second loading condition of the computing device; and a second circuitry to detect a potential fault in a cooling system to cool the computing device, based at least in part on the first temperature and the second temperature.

Temperature sensing based flow monitoring and fault detection

Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may be capable of time stamping information related to ingress request and egress response packets for a transaction. For these examples, elements of the server may be capable of determining transaction latency values based on the time stamped information. The determined transaction latency values may be used to monitor or manage operating characteristics of the server to include an amount of power provided to the server or an ability of the server to support one or more virtual servers. Other examples are described and claimed.

Techniques associated with server transaction latency information

Apparatus and methods may provide for characterizing a plurality of similar components of a distributed computing system based on a maximum safe operation level associated with each component and storing characterization data in a database and allocating non-uniform power to each similar component based at least in part on the characterization data in the database to substantially equalize performance of the components.

Mitigating component performance variation

Mechanisms for exposing a protected memory address are provided. A processing device may store a data value at a protected memory address. The protected memory address may be a control register or a status register. The processing device may identify a mirror relationship between the protected memory address and an unprotected memory address and copy the data value from the protected memory address to the unprotected memory address. The unprotected memory address may be directly accessible via an external interface.

Exposing protected memory addresses

Growing community of inventors

Chandler, AZ, United States of America

Ramkumar Nagappan