Intel Corporation

Ramkarthik Ganesan

Shankar Natarajan

Owen W Jungroth

Sanjay S Talreja

Suresh Nagarajan

Sriram Natarajan

Romesh B Trivedi

Arun Sitaram Athreya

Saad Monasa

Pranav Kalavade

Lance W Dover

Xin Guo

Terry L Kendall

Eugene P Matter

Ning Wu

Robert Frickey

Ramadurai Rajagopal

Jason Panavich

Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.

Block management for dynamic single-level cell buffers in storage devices

Technology for an apparatus is described. The apparatus can include a first non-volatile memory, a second non-volatile memory to have a write access time faster than the first non-volatile memory, and a memory controller. The memory controller can be configured to detect corrupted data in a selected data region in the first non-volatile memory. The selected data region can be associated with an increased risk of data corruption after data is written from the second non-volatile memory to the first non-volatile memory. Uncorrupted data in the second non-volatile memory that corresponds to the corrupted data in the first non-volatile memory can be identified. Data recovery in the first non-volatile memory can be performed by replacing the corrupted data in the first non-volatile memory with uncorrupted data from the second non-volatile memory.

Data recovery in memory devices

A Double Data Rate (DDR) nonvolatile memory for use with a wireless device. A host processor transfers commands and data through a DDR interface of the nonvolatile memory. The DDR nonvolatile memory implements legacy flash functions while maintaining DDR behavior.

DDR flash implementation with direct register access to legacy flash functions

A Double Data Rate (DDR) nonvolatile memory includes a DDR I/F block to receive an address that is used to separate DDR data into coherent data and non-coherent data that are stored separately in the DDR nonvolatile memory.

DDR flash implementation with hybrid row buffers and direct access interface to legacy flash functions

A method, apparatus, and system for controlling the voltage levels across capacitors coupled between a first node and a second node of an integrated circuit so that the voltage levels across these capacitors will not exceed the breakdown voltage limitation of these capacitors. The voltage level between the first and second nodes of the integrated circuit can vary from a second voltage level to a first voltage level when the integrated circuit transitions from a second power state to a first power state, respectively. A first capacitor and a second capacitor are connected in series between the first and second nodes of the integrated circuit forming a middle node between the first and second capacitors. The voltage level of the middle node is set to a third voltage level when the integrated circuit is placed in the first power state such that the voltage level between the first and middle nodes doesnotexceed the breakdown voltage of the first capacitor and the voltage level between the middle and second nodes does not exceed the breakdown voltage of the second capacitor.

Method and apparatus for reducing stress across capacitors used in integrated circuits

Briefly, in accordance with one embodiment of the invention, a portable communication device may have multiple processors and a memory. Portions of the memory may only be accessible by one of the processors.

Memory adapted to provide dedicated and or shared memory to multiple processors and method therefor

A single status register, capable of providing status for simultaneous read-while-write operation on a flash memory array is described. The status of the memory array is reported to the user based on two partitions. A microcontroller is used to traffic the status register to memory array communication.

Status register architecture for flexible read-while-write device

A burst transfer operation with a memory device can be suspended and resumed without having to provide the current memory address when it is resumed. A chip enable signal to the memory device can be deasserted to initiate the suspend operation and place the memory device in a low power standby mode. When the chip enable signal is reasserted, the memory device can be reactivated and the burst transfer can continue where it stopped, without any setup commands. The current address counter and other bus transfer parameters can be saved within the memory device during the suspend operation. When the suspend operation is terminated by reasserting the chip enable signal, the memory device can resume the transfer using the saved parameters.

Burst suspend and resume with computer memory

A method, apparatus, and system for controlling the voltage levels across capacitors coupled between a first node and a second node of an integrated circuit so that the voltage levels across these capacitors will not exceed the breakdown voltage limitation of these capacitors. The voltage level between the first and second nodes of the integrated circuit can vary from a second voltage level to a first voltage level when the integrated circuit transitions from a second power state to a first power state, respectively. A first capacitor and a second capacitor are connected in series between the first and second nodes of the integrated circuit forming a middle node between the first and second capacitors. The voltage level of the middle node is set to a third voltage level when the integrated circuit is placed in the first power state such that the voltage level between the first and middle nodes does exceed the breakdown voltage of the first capacitor and the voltage level between the middle and second nodes does not exceed the breakdown voltage of the second capacitor.

Growing community of inventors

Folsom, CA, United States of America

Ramkarthik Ganesan