Ikanos Communications, Inc.

Hitachi America, Ltd.

Velocity Communication, Inc.

Blue Vector Systems

Raminder Singh Bajwa

Behrooz Rezvani

Avadhani Shridhar

Sam Heidari

Omprakash S Sarmaru

Dale Smith

Firooz Massoudi

Masoud Eskandari

Sridhar Begur

Jacky S Chow

Anurag Mendhekar

T R Ramesh

John Gevargiz

Tiruvur R Ramesh

Saman Behtash

Sanjeev Dharap

Sam Heid Ari

Pavithra Reddy Moranganti

Radhika Muralidharan

Prem Ramaswamy

A bidirectional radio frequency identification (RFID) network system and method are presented. The system allows users to configure, monitor, and manage different sensor devices by using a graphical user interface real-time. The reconfiguration is done through a network management computer at the top system level that receives user input, generates code images according to the user input, and appropriately routes the code images to sensor routers that directly control the sensors. If the system is multi-layered, some code images are also sent to the intermediate-level network management computers. The system allows users to not only monitor a business flow but react to problematic situations quickly by adjusting the workflow. The aspect-oriented nature of the system allows users to reconfigure the system based only the Functionality aspects without worrying about the Partitioning aspects (e.g., how the network and the sensors are physically connected).

Radio frequency identification (RFID) network system and method

A transceiver for communicating a multi-tone modulated communication channel on a subscriber line. The transceiver includes: a digital signal processor (DSP) with a Fourier transform module and an analog front end (AFE). The DSP determines an available range of frequencies on the subscriber line and expands or contracts the tone spacing of each of a fixed number 'N' of tones accordingly by decreasing or increasing the processing interval associated with the Fourier transform of each tone set. The AFE performs digital-to-analog conversion of the multi-tone modulated communication channel at rates compatible with the processing interval of the Fourier transform module; whereby the range of frequencies spanned by the modulated tones on the subscriber line conforms to the available of frequencies on the subscriber line.

Method and apparatus for a variable bandwidth multi-protocol X-DSL transceiver

The current invention provides a method and apparatus for time domain equalization in an XDSL modem. A received communication channel is analyzed to determine the highest frequency component thereof. Typically, there is an inverse relationship between the length of a subscriber line and the highest frequency component over which communications can be supported. In response to the frequency determination, the sampling rate for the channel is reduced to the lowest sample rate consistent with maintaining signal integrity on the highest frequency component of the channel. The sampling rate reduction may accomplished in the analog portion of the receive path, e.g. the analog-to-digital converter (ADC) or in a digital decimator coupled thereto. Concurrently the demodulator complexity is also scaled back. Where the XDSL protocol is digital multi-tone (DMT) the input sample size to the discrete Fourier transform (DFT) engine is reduced accordingly. With these adjustments in place TEQ resources may be scaled inversely. Thus as line length increases and the available bandwidth on the subscriber line is reduced more TEQ resources are made available to deal with the increased delay interval over which intersymbol interference is evidenced. Scaling of TEQ resources may be accomplished using a TEQ architecture which allows either the length or the tap line or the delay between taps to be varied.

Method and apparatus for time domain equalization in an XDSL modem

A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

Method and apparatus for a DFT/IDFT engine supporting multiple X-DSL protocols

The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc. The present invention provides a signal processing architecture that supports scalability of CO/DLC/ONU resources, and allows a significantly more flexible hardware response to the evolving X-DSL standards without over committing of hardware resources. As standards evolve hardware may be reconfigured to support the new standards.

Method and apparatus for a X-DSL communication processor

The current invention provides a digital signal processor which supports multiple X-DSL protocols and a multiplicity of channels on a single chip. Each channel is packetized and each packet includes control information for controlling the performance of the components/modules on the transmit and receive path. Further flexibility is derived from an architecture which incorporates discrete and shared modules on the transmit path and the receive path. The transmit path and receive path modules are collectively controlled by control information in selected ones of the packets and operate on each channel's packets at an appropriate rate, and protocol for the channel. A digital signal processor (DSP) is disclosed which incorporates these features. The DSP exhibits a favorable form factor, and flexibility as to protocols and line codes, and numbers of channels supported.

Method and apparatus for synchronizing a packet based modem supporting multiple X-DSL protocols

The apparatus includes a first SOVA decoder that generates a first path reliability value from a channel value, a parity symbol and a first a priori likelihood value. A first decorrelation unit generates a first extrinsic symbol reliability value by decorrelating the channel value and the first a priori likelihood value from the path reliability value. A first symbol reliability saturation unit saturates the first extrinsic symbol reliability value to generate a first saturated extrinsic symbol reliability value. A first interleaver interleaves the first saturated extrinsic symbol reliability value to generate a second a priori likelihood value. A second interleaver interleaves the channel value to generate an interleaved channel value. A second SOVA decoder generates a second path reliability value from an interleaved parity symbol, the second a priori likelihood value, and the interleaved channel value. A second decorrelation unit generates a second extrinsic symbol reliability value by decorrelating the interleaved channel value and the second a priori likelihood value from the second path reliability value. A second symbol reliability saturation unit saturates the second extrinsic symbol reliability value to generate a second saturated extrinsic symbol reliability value. A first de-interleaver de-interleaves the second saturated extrinsic symbol reliability value to generate the first a priori likelihood value. A second de-interleaver de-interleaves the second extrinsic symbol reliability value to generate a decoded message. Additionally, the path reliability value are saturated. Advantages include simplified hardware implementations having improved BER characteristics and faster convergence, requiring fewer decoding iterations to generate a result.

Method and apparatus for turbo-code decoding a convolution encoded data frame using symbol-by-symbol traceback and HR-SOVA

The present invention is directed to a digital signal processor having a local buffer for storing decoded instruction words during the first pass through a program loop, so that subsequent iterations through the program loop can be accomplished without the use of the instruction fetch and decode circuitry, thereby saving power.

Decoded instruction buffer apparatus and method for reducing power

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Palo Alto, CA, United States of America

Raminder Singh Bajwa