Altera Corporation

Viciciv Technology

Tier Logic, Inc.

Other

Callahan Cellular L.l.c.

Semiconductor Components Industries, LLC

Viciciv, Inc.

Altera Coporation

Airip Corporation

Raminda U Madurawe

James D Sansbury

Richard G Smolen

John E Turner

Peter John McElheny

Seshan Sekariapuram

Rakesh H Patel

Dominik J Schmidt

Myron Wai Wong

John C Costello

Peter J Wright

Christopher J Pass

Minchang Liang

Irfan Rahim

Nij Dorairaj

Richard A Mauritzson

Thomas Henry White

David K Y Liu

Charu Sardana

William George Gazeley

Francois Gregoire

Bruce F Mielke

Hamid Soleimani

Peter Ramyalal Suaris

Guru Thalapaneni

Bruce E Mielk

Bruce E Mielke

A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

Stacked-die image sensors with shielding

In one embodiment, a method of forming a semiconductor device may include extending a gate conductor of a transistor to overlie a boundary of a well region in which the transistor is formed. The gate conductor may extend to make electrical contact with a gate conductor of a 2nd transistor that is formed external to the well region. A contact conductor may be applied to electrically and physically contact the first and 2nd gate conductors and to also overlie the boundary of the well region.

Method of forming a semiconductor device

An image sensor may include an array of pixels, and analog and digital circuitry. The pixels in the array may generate image signals in response to incident light. The image sensor may also include power supply circuitry and corresponding voltage rail structures that provide voltage levels to operate the pixel array, the analog circuitry, and the digital circuitry. The power supply circuitry may provide a low voltage, a high voltage, and an intermediate voltage power rail. The analog circuitry may operate in a voltage level domain defined by voltages between an intermediate voltage level and a high voltage level. The digital circuitry may operate in a voltage level domain defined by voltages between a low voltage level and the intermediate voltage level. In such a configured, analog and digital circuitry may both be provided with low-voltage transistors that are more area and power efficient and that are more scalable.

Image sensors with low-voltage transistors

A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

Programmable structured arrays

A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

Three dimensional integrated-circuits

A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.

Timing exact design conversions from FPGA to ASIC

A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.

Pads and pin-outs in three dimensional integrated circuits

An imaging system may include multi-port pixels. A multi-port pixel may include a photodiode that generates electrical charge in response to received light and a plurality of access ports that couple the electrical charge onto one of a corresponding plurality of pixel output lines. The photodiode may generate electrical charge for one or more different integration times while a frame is being captured. Charge generated during the different integration times may be coupled onto different respective pixel output lines through different respective access ports. Multiple pixels in a given column of the pixel array may simultaneously couple charge generated during different integration times onto different pixel output lines through different access ports.

Multi-port image pixels

Three dimensional integrated circuits

An integrated circuit die may include bottom-gate thin-body transistors. The bottom-gate thin-body transistors may be formed in a thinned-down substrate having a thickness that is defined by shallow trench isolation structures that provide complete well isolation for the transistors. The transistors may include gate terminal contacts formed through the shallow trench isolation structures, bulk terminal contacts that are formed through the thinned substrate and that overlap with the gate contacts, and source-drain terminal contacts with in-situ salicide. Additional metallization layers may be formed over the gate/bulk/source-drain contacts after bonding.

Bottom-gate thin-body transistors for stacked wafer integrated circuits

An image sensor with an array of pixels is provided. To minimize optical and electrical and crosstalk, the array of pixels may include deep trench isolation structures interposed between adjacent pairs of photodiodes. In order to maximize quantum efficiency, the array of pixels may include a reflective stack formed under the photodiodes and the deep trench isolation structures. The deep trench isolation structures may be formed from doped glass, doped polysilicon, or metal having a doped oxide liner. The reflective stack may include multiple layers of materials having different indices of refraction. The reflective stack may include oxide, nitride, and semiconductor layers. The deep trench isolation structures may extend from the top of the photodiodes down to the reflective stack. The deep trench isolation structures may have a 50 to 1 aspect ratio.

High efficiency image sensor pixels with deep trench isolation structures and embedded reflectors

Growing community of inventors

Sunnyvale, CA, United States of America

Raminda U Madurawe