Huawei Technologies Co., Limited

Rami Zecharia

Alex Umansky

Yan Wang

Alex Tal

Shlomo Reches

Yaron Shachar

Yuval Elad

Zion Gal

A method and devices for reducing the delay in end-to-end delivery of network packets may be achieved by having the transmission (TX) side of the device, tag each cell with a unique packet identifier and with a byte offset parameter where the tagging allows the reception (RX) side of the destination device to perform on-the-fly assembly of cells into packets by directly placing them at corresponding host buffer, and the method may be done for multiple packets concurrently, and hence store and forward buffering is not needed in either the source or the destination devices and the lowest possible end-to-end cut-through latency is achieved.

Transmission and reception devices

A method for packet reassembly and reordering, comprising: receiving a cell sent by a source port, wherein the cell carries a Source Identification (SID), a packet sequence number and a cell sequence number; preprocessing the received cell according to the SID to determine whether the cell shall be inserted into a packet reassembly database; ordering cells in the packet reassembly database according to the packet sequence number to obtain a correctly ordered packet; if the correctly ordered packet is a complete packet, ordering the cells of the correctly ordered packet according to the cell sequence number to obtain correctly ordered cells; and performing a packet reassembly for the correctly ordered cells. Correspondingly, a network device and a communication system are provided.

Method, apparatus and system for packet reassembly and reordering

A memory system () comprising a control logic () adapted to receive a number n of write requests (WRs) from input ports and to receive a read request (RR) from an output port within a clock cycle of a clock signal (CLK) applied to said memory system (), wherein n is a natural number; and n+1 memory banks () of a shared memory () adapted to store data, wherein the control logic () is adapted to control a memory bank occupancy level MBOL of each memory bank () such that the differences between memory bank occupancy levels MBOLs of the memory banks () are minimized.

Memory system and an apparatus

Growing community of inventors

Munich, Germany

Rami Zecharia