National Semiconductor Corporation

Rami Saban

Alon Shacham

Avner Efendovich

Varda Karpati

Peleg Lior

Dan Biran

Aharon Ostrer

Yomtov Sidl

Yomtov Sidi

Gigi Baror

Moti Beck

Benny Konstantin

Jonanthan Levy

Elliot Cohen

Yair Hadas

Alon Shackam

Boaz Shahar

A testability architecture and method for loosely integrated (modularized) integrated circuits uses stand alone module testing. For an integrated circuit chip which has a number of independent modules, where one module design is used in a number of different chips, each module is connected to the chip's input/output pins and to a configuration module. To make testing of the modules more efficient and less expensive, during testing of the chip a particular module design is confronted with the same testing environment regardless of the actual chip in which it is present. Advantageously, chip area is only slightly enlarged by the test circuitry. A test architecture of the configuration module includes test registers and carries out a standard protocol for all read and write transactions during testing. This approach provides better test coverage and economizes in test generation.

Testability architecture for modularized integrated circuits

Testability method for modularized integrated circuits

The data separator of this invention may be used for extracting clock and data signals from a serial stream of bits read from a magnetic disk or tape. The data separator is supplied with a 'fast' clock pulse generated by a frequency multiplexer. After a lock indication from the frequency multiplier, during the first eight serial data pulses the frequency and phase of the data separator are synchronized to the serial data pulses. Then an early and late logic unit keeps track digitally of the cumulative phase difference between the incoming data stream and the output of the data separator. When the cumulative phase difference reaches predetermined limits, the phase of the output is adjusted. If a second phase adjustment is required in the same direction (i.e., early or late), the frequency of the output is adjusted. The output of the data separator is generated by a decrementing register, the phase or frequency of the data separator being adjusted by increasing or decreasing the initial value loaded into the decrementing register. The data separator is fully digital.

Fully digital data separator and frequency multiplier

A frequency multiplier includes a ring oscillator having a number of logic gates arranged in a plurality of rings. Control inputs enable the selection of individual gates so as to connect them into the ring or, conversely, remove them from the ring. As additional gates are removed, the combined delay imposed by the gates remaining in the ring is reduced and the frequency of the oscillator increases. A variable delay element, preferably a group of tri-state inverters connected in parallel, is connected between two of the gates. The oscillator is fine tuned by controlling the delay inserted by the variable delay element. The frequency multiplier also includes a frequency comparator. A reference frequency is passed through a divide-by-K unit and the output of the ring oscillator is passed through a divide-by-N unit, N being greater than K. The frequency multiplier is coarse-tuned by progressively removing additional gates from the ring oscillator, and then fine-tuned by increasing the delay imposed by the variable delay element. At the conclusion of coarse and fine tuning, the frequency multiplier is locked at a frequency which closely approximates a reference frequency multiplied by N/K. An accuracy of 1% or less may be achieved. When the frequency multiplier ceases to be hooked on a frequency, it enters an idle state in which it consumes no power.

Digital frequency multiplier utilizing digital controlled oscillator

A method and apparatus for prechecking (probing) the validity of an access request for writing result data to an external system prior to executing the instruction that generates the result is provided. This allows instruction execution to continue uninterrupted in the event that the write is allowed. The microprocessor's Address Unit issues a 'probe' request to the Memory Management Unit (MMU) via an internal bus while saving the instruction's virtual address in a virtual address buffer local to the Address Unit. The MMU checks the validity of the 'probe' request without converting the virtual address to a physical address and issues an access grant signal which is saved by the microprocessor's Execution Unit for subsequent use. The Execution Unit processes the data in parallel to the MMU checking the validity of the probe request. If the virtual address associated with the probe request resulted in an access grant signal, then the Execution Unit issues a write request while the virtual address previously stored in the Address Unit is sent to the MMU for translation to a physical address. Both the write data and the physical address are stored in a buffer in the microprocessor's Bus Interface Unit (BIU) for subsequent transfer to an external system. The data is then written to the external system at the physical address provided by the BIU.

Method of prechecking the validity of a write access request

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Holon, Israel

Rami Saban