Motorola Corporation

Rami Natan

Vitaly Sukonik

Alex Miretsky

James B Eifert

Wallace B Harwood, Iii

Avi Ginsberg

Arie Ben-Ephraim

Amit Dor

Alexander Miretsky

Arie Kazachin

Yossi Asher

An apparatus and a method for providing decoded information, the apparatus comprising: a memory module for storing encoded information; a decoder, coupled to the memory module, for fetching and decoding encoded information and for providing decoded information; and a cache, coupled to the memory module and to the decoder and to a recipient of decoded information, the cache is adapted to store at least one set of decoded information, to be provided to the recipient of information after a cache check condition is fulfilled and a cache hit occurs. A cache check condition is fulfilled when a change of flow occurs.

Apparatus and a method for providing decoded information

A computer and a method are described having multiple pointers for a branch instruction. A branch target instruction called by the branch instruction is divided into H parts locatable by K pointers. L of the K pointers are stored in the branch instruction and K-L pointers are stored with the H parts of the branch target instruction. A tag identifies a variable boundary between first and second halves of the memory, word by word. The first half of the memory space contains V of H parts of the instructions and the second half of the memory space contains the H-V parts. The parts in the first and second halves of the memory space are compressed and decompressed in parallel.

Computer system having a multi-pointer branch instruction and method

A converter (,) comprises a multiplex-buffer (,) at a bus (,), a decoder (,), an output buffer (,) and a comparator (,). The multiplex-buffer (,) forwards V,bits (,) of Huffman coded code portions (,) from the bus (,) to the decoder (,). The V,bits (,) can comprise further bits set to logical &ldquo;1&rdquo; or &ldquo;0&rdquo; at random. On a control output (,), the multiplex-buffer (,) provides a signal K identifying which of the V,bits are valid or invalid. The decoder (,) maps the V,bits (,) into a preliminary bit cluster (,) and indicates a code length V regardless whether some or all bits are valid or not. The comparator (,) checks V and K and allows the output buffer (,) to copy the preliminary bit cluster (,) into instruction portions (,) only when the code length fits the identification of valid bits.

System for converting instructions, and method therefore

A data processing system (20) has a central processing unit (CPU) (22) and a memory (30) for storing an exception table. The exception table is mapped in the memory (30) in consecutive segments, with each segment for storing a predetermined number of instructions for executing the exception. By asserting a control bit, the exception table can be relocated, or remapped, and compressed into a jump table. The jump table stores only jump instruction for branching to the exception routines, which are relocated to other memory locations. The jump table is generated from the starting addresses of the exception routines. Relocating the exception routines allows for more efficient use of internal memory space of the data processing system (20).

Data processing system having selectable exception table relocation and

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Ramat Gan, Israel

Rami Natan