Intel Corporation

Other

Mcafee, Inc.

Rameshkumar G Illikkal

Sadagopan Srinivasan

Srihari Makineni

Jaideep Moses

Donald K Newell

Li Zhao

Gregory Cummings

Carl R Strathmeyer

Donald K Finnie

Hugh P Mercer

Yong Zhang

Andrzej Kuriata

Teck Joo Goh

Bounthavivone K Phomsopha

Francesc Guim Bernat

Kshitij Arun Doshi

Ravi L Sahita

Rajesh Poornachandran

Martin Guy Dixon

Michael E Kounavis

Qian Li

Francis X Mckeen

Vincent R Scarlata

Ravishankar Iyer

Andrew J Herdrich

Carl S Marshall

Avinash N Ananthakrishnan

Quinn Able Jacobson

Howard C Herbert

Selvakumar Panneer

Simon R Hunt

Katalin Klara Bartfai-Walcott

Krystof C Zmudzinski

Jianping Zhou

David Zimmerman

Sridhar Muthrasanallur

Mingqiu Sun

Mona Vij

Ashish V Choubal

Rajesh Sankaran Madukkarumukumana

Slawomir Putyrski

Pratik M Marolia

Dave B Minturn

Nilesh K Jain

Saul Lewites

Ulhas S Warrier

Zhen Fang

Venkata Ramanan Sambandam

Suresh Srinivas

Ramakrishna Huggahalli

Erik Hallnor

Bin Li

Mark E Scott-Nash

Carlos Carrizo

Xiaowei Jiang

David Novick

Jennifer Eligius Mankin

Mark P Baldwin

Anjo Lucas Vahldiek-Oberwagner

Krishna Surya

Samuel Ortiz

Vijay S R Degalahal

Ramanan V Ganesan

Haidong Xia

Ananth Sankaranarayanan

Jared E Bendt

Zhaorong Hou

Wenhui Shu

Suchit Subhaschandra

Michael Steiner

Sudha Krishnakumar

Carl Lebsack

Ian Taylor

Anna Drewek-Ossowicka

Daniel Richins

Long Cui

Mourad Cherfaoui

Jinshi Chen

Dayeol Lee

Dharmisha Ketankumar Doshi

Mihai Daniel Dodan

Bryan Hunt

Michael Beale

Srinivas Sundaravaradan

Francisco M Casares

Sadogopan Srinivasan

Mihai-Daniel Dodan

Dmitrii Kuvaiskii

Thomas Knauth

David O Novick

Various approaches to efficiently allocating and utilizing hardware resources in data centers while maintaining compliance with a service level objective (SLO) specified for a computational workload is translated into a hardware-level SLO to facilitate direct enforcement by the hardware processor, e.g., using a feedback control loop or model-based mapping of the hardware-level SLO to allocations of microarchitecture resources of the processor. In some embodiments, a computational model of the hardware behavior under resource contention is used to predict the application performance (e.g., as measured in terms of the hardware-level SLO) to be expected under certain contention scenarios. Scheduling of workloads among the compute nodes within the data center may be based on such predictions. In further embodiments, configurations of microservices are optimized to minimize hardware resources while meeting a specified performance goal.

Efficient resource allocation for service level compliance

In function-as-a-service (FaaS) environments, a client makes use of a function executing within a trusted execution environment (TEE) on a FaaS server. Multiple tenants of the FaaS platform may provide functions to be executed by the FaaS platform via a gateway. Each tenant may provide code and data for any number of functions to be executed within any number of TEEs on the FaaS platform and accessed via the gateway. Additionally, each tenant may provide code and data for a single surrogate attester TEE. The client devices of the tenant use the surrogate attester TEE to attest each of the other TEEs of the tenant and establish trust with the functions in those TEEs. Once the functions have been attested, the client devices have confidence that the other TEEs of the tenant are running on the same platform as the gateway.

Scalable attestation for trusted execution environments

An apparatus and method for dynamic resource allocation with mile/performance markers. For example, one embodiment of a processor comprises: resource allocation circuitry to allocate a plurality of hardware resources to a plurality of workloads including priority workloads associated with one or more guaranteed performance levels; and monitoring circuitry to evaluate execution progress of a workload across a plurality of nodes, each node to execute one or more processing stages of the workload, wherein the monitoring circuitry is to evaluate the execution progress of the workload, at least in part, by reading progress markers advertised by the workload at the specified processing stages, wherein the monitoring circuitry is to detect that the workload may not meet one of the guaranteed performance levels based on the progress markers, and wherein the resource allocation circuitry, responsive to the monitoring circuitry, is to reallocate one or more of the plurality of hardware resources to improve the performance level of the workload.

Apparatus and method for a resource allocation control framework using performance markers

Various embodiments for dynamically generating an advertisement in a video stream are disclosed. In one embodiment, video stream content associated with a video stream for a user device is received. Video analytics data is obtained for the video stream content, which indicates a scene recognized in the video stream content. An advertisement to be generated and inserted into the video stream content is then selected based on the scene recognized in the video stream content, and an advertisement template for generating the selected advertisement is obtained. Video advertisement content corresponding to the advertisement is then generated based on the advertisement template and the video analytics data. The video advertisement content is then inserted into the video stream content, and the modified video stream content is transmitted to the user device.

On-demand generation and personalization of video content

Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.

Systems and methods for accessing storage-as-memory

In an example, there is disclosed a computing apparatus, having a computing resource; a bespoke sensor for measuring at least one parameter of usage of the computing resource; and one or more logic elements providing a trusted compute meter (TCM) agent to: receive an external workload; provision a workload enclave; execute the external workload within the TCM enclave; and measure resource usage of the external workload via the bespoke sensor. There is also disclosed a computer-readable medium having stored thereon executable instructions for providing a TCM agent, and a method of providing a TCM agent.

Trusted computing resource meter

In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

Power efficient processor architecture

An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.

Interrupt return instruction with embedded interrupt service functionality

Methods and apparatus for efficient peer-to-peer communication support in interconnect fabrics. Network interfaces associated with agents are implemented to facilitate peer-to-peer transactions between agents in a manner that ensures data accesses correspond to the most recent update for each agent. This is implemented, in part, via use of non-posted 'dummy writes' that are sent from an agent when the destination between write transactions originating from the agent changes. The dummy writes ensure that data corresponding to previous writes reach their destination prior to subsequent write and read transactions, thus ordering the peer-to-peer transactions without requiring the use of a centralized transaction ordering entity.

Efficient peer-to-peer communication support in SoC fabrics

Systems, methods, and apparatus to configure embedded devices are described. An example apparatus includes a network interface to communicatively couple the apparatus with a network, an antenna to receive a radio frequency signal including 1) configuration data and 2) power, a memory coupled to the antenna to receive the power and to store the configuration data, a network configurer to retrieve the configuration data from the memory and to configure the network interface based on the retrieved data, and a power source other than the antenna to provide power to the memory and the network configurer during operation of the network configurer.

Systems, methods, and apparatus to configure embedded devices

Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.

Optimized fast hessian matrix computation architecture

Growing community of inventors

Portland, OR, United States of America

Rameshkumar G Illikkal