Intel Corporation

Ramesh Subashchandrabose

Rajat Agarwal

Tessil Thomas

Kai Cheng

Debaleena Das

Sambaran Mitra

Anupam Mohanty

Tonia G Morris

Lohit R Yerva

Moshe Jacob Finkelstein

Techniques and mechanisms for providing communications which facilitate link training. In an embodiment, a memory controller includes, or couples to, trainer circuitry which is configured to provide instructions to generate memory access commands. The instructions are accessed at the circuitry in response to an indication that link training is performed, where the accessing is independent of communication with a processor coupled to the memory controller. Based on the instructions, memory access commands are communicated via a link between the memory controller and a memory device. Link training is performed based on an evaluation of one or more characteristics of the link communications. In another embodiment, memory access commands are generated, based on the instructions, while a validity of data at the memory device is maintained.

Device, system and method to generate link training signals

Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Rank-specific cyclic redundancy check

In some embodiments, a chip includes chip interface transmitters, a chip, and clock gearing logic. The transmitters are to transmit signals in frames including slots. The scheduler is to schedule signals at a first frequency including commands for first slots of the frames in general and commands for second slots of at least some frames immediately preceding frequency mismatch bubbles occurring when the frames are at a second frequency. The clock gearing logic is to provide the signals having the first frequency from the scheduler to the transmitters at the second frequency. Other embodiments are described.

Commands scheduled for frequency mismatch bubbles

According to one embodiment, a system is disclosed. The system includes a memory controller to schedule read commands to frames via a first dedicated command slot and to schedule write commands and corresponding data to frames via a dedicated second or third command slot.

Growing community of inventors

Bengaluru, India

Ramesh Subashchandrabose