Synopsys, Inc.

Tharas Systems Inc.

Eve S.a.

Other

Ramesh Narayanaswamy

Subbu Ganesan

Ian Michael Nixon

Leonid Alexander Broukhis

Thomas Hanni Spencer

Subramanian Ganesan

Dinesh Madusanke Pasikku Hannadige

Paraminder S Sahai

Alexander Rabinovitch

Subha S Chowdhury

Chiahon Chien

Anil Nagori

Chanaka Ranathunga

Aditha Pabasara Rajakaruna

A processing system for validating a circuit design, the processing system includes a flow processor, and an evaluation system coupled with the flow processor. The flow processor generates instructions from the circuit design. The evaluation system includes instruction memory circuitry receives the instructions from the flow processor and generate control signals, and interconnect circuitry receives the control signals routes a plurality of values based on the control signals. Each of the plurality of values having one of four states. The evaluation further includes operation circuitry that receives the plurality of values and the control signals, performs one or more operations of the circuit design with the plurality of values based on the control signals, and outputs operation values based on performing the one or more operations, the operation values indicative of an error within the circuit design.

Clock aware simulation vector processor

This disclosure describes an apparatus and method for simulating circuit designs. An apparatus for simulating circuit designs includes a first simulation vector processor (SVP) and a second SVP communicatively coupled to the first SVP. The first SVP simulates a first portion of a circuit design under test. The second SVP simulates the first portion of the circuit design under test at least partially while the first SVP simulates the first portion of the circuit design and asynchronously with the first SVP and transmits data to the first SVP while simulating the first portion of the circuit design, wherein the first SVP uses the data while simulating the first portion of the circuit design.

Message passing multi processor network for simulation vector processing

Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design.

Selective execution for partitioned parallel simulations

Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values of the circuit design which do not depend on a clock signal, and a clock propagation stage in which the system evaluates signal values that depend on a clock signal. Some embodiments of the present invention sample signal values during the stimuli application stage, and use the sampled signal values during the clock propagation stage to handle race conditions in state elements and/or glitches in clock trees that may occur during logic simulation.

Logic simulation and/or emulation which follows hardware semantics

An approach for simulating a circuit design partitions the circuit design into pipeline regions that include one or more pipeline levels. A path length is computed for each combinational region within a pipeline region to compute an achievable timing goal for each pipeline region. A target retiming goal is determined for the set of pipeline regions based on the computed achievable timing goals of the pipeline regions. A pipeline region is identified from the set of pipeline regions that does not satisfy the target timing goal. A measure of slack is computed for each pipeline level in the identified pipeline region. Using the computed slack, path lengths of combinational regions in the pipeline levels of the identified pipeline region are iteratively retimed. The resulting circuit design is simulated using the retimed path lengths if the retimed critical path of the pipeline region satisfies the target timing goal.

Retiming a design for efficient parallel simulation

An approach for simulating an electronic circuit design uses the influence of a set of input changes of regions of the circuit design to schedule which levels within regions of a circuit should be simulated. The state of one or more inputs of one or more regions of the circuit design is checked to determine if inputs to these regions changed. For each input having an input change, a logic level depth associated with the input is computed. Using the computed logic levels, a maximum logic level depth of the one or more regions is computed for a set of input changes. Thus, for each region that has an input with a state indicating an input change, simulation may be scheduled for first logic level through and including the determined maximum logic level in each region of the circuit design in parallel.

Quasi-dynamic scheduling and dynamic scheduling for efficient parallel simulation

An RTL hardware description language simulation accelerator and circuit emulator which operates on data driven asynchronous completion handshaking principles. Deploying Muller C elements to control latches, the system does not depend on externally provided clocks or internal timing circuits with delay logic or clock generators. Each levelized domain of logic signals a successor level to begin execution of instructions with a level complete message produced when all its input operands have produced a completion message. Each predecessor stage holds back data production until the successor stage is ready. Each levelized data-driven asynchronous domain evaluation processor is self-timed receiving completion messages from its predecessors, and sending completion messages to its successors.

Method for delay immune and accelerated evaluation of digital circuits by compiling asynchronous completion handshaking means

A scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.

Scalable system for simulation and emulation of electronic circuits using asymmetrical evaluation and canvassing instruction processors

A logic simulation acceleration processor optimized for multi-value logic level simulation of electronic systems described in hardware description languages.

Compact processor element for a scalable digital logic verification and emulation system

A functional verification system suited for verifying the function of non-cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Functional verification system

Functional verification system enabling the state of difference signals to be traced. The signals represent the outputs resulting from the evaluation of combinatorial blocks and/or a plurality of state elements forming a target design. The combinatorial blocks and/or a plurality of state elements may be grouped into multiple clusters, with each cluster being identified by a cluster identifier. The tracing circuit may include a mask memory, a previous state memory, and trace controller. Each of the mask memory and the previous state memory may contain a number of locations equal to the number of clusters such that the relevant mask and previous state information may be accessed based on the cluster identifier. The trace controller receives evaluated outputs for a cluster at bit positions specified by a corresponding mask. The trace controller compares the received bits with the previous values, and generates an entry in a trace buffer to record any changes.

Tracing the change of state of a signal in a functional verification system

A run time controller which controls the sequence of evaluations of combinatorial blocks in a functional verification system. A target design is partitioned into multiple clusters, with each cluster in turn containing multiple combinatorial blocks. Evaluation units may be designed to evaluate the combinatorial blocks in each cluster in parallel. The run time controller may contain a flow processor, a flow control memory, and a cluster control memory. The contents of cluster control memory may be configured to specify how different condition bits/registers are to be altered upon evaluation of each cluster. The flow control memory is configured with instructions to data from different sources to be sent the evaluation units. In addition, the instructions are designed to examine the status of different registers and cause the flow processor to alter the evaluation flows.

Run-time controller in a functional verification system

A functional verification system which can be used to evaluate either cycle based designs or non-cycle based designs. A target design is partitioned into multiple clusters, with a combinatorial block in each cluster being assigned to an evaluation unit. A flow control memory stores data indicating the sequence in which the clusters are to be evaluated. The evaluation units evaluate combinatorial blocks within a cluster in parallel. A cluster control memory indicates the manner in which a register is to be modified upon the evaluation (and results) of each cluster. The instructions in the flow control memory may be designed to examine the contents of the register and evaluate the clusters in different sequences depending on the content of the register. Evaluation of a loop of a non-cycle based design can thus be terminated based on the contents of the register.

Functional verification of both cycle-based and non-cycle based designs

A functional verification system which provides information as to whether a signal has reached all possible states. For example, in the case of a signal with 0 and 1 as possible states, a 2 bit variable is initialized to 00. When a value of 1 is received for the signal, the first bit is set to 1 and when a value of 0 is received for the signal, the second bit is set to 1. Accordingly, by examining the two bits, one may determine whether the signal has attained one or both of 0 and 1 states.

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Palo Alto, CA, United States of America

Ramesh Narayanaswamy